Re: [Intel-gfx] [PATCH 03/13 v4] drm/i915: Add GuC-related header files
On Tue, Jul 21, 2015 at 08:38:35AM +0200, Daniel Vetter wrote: On Fri, Jul 17, 2015 at 05:38:05PM -0700, O'Rourke, Tom wrote: On Thu, Jul 09, 2015 at 07:29:04PM +0100, Dave Gordon wrote: intel_guc_fwif.h contains the subset of the GuC interface that we will need for submission of commands through the GuC. These MUST be kept in sync with the definitions used by the GuC firmware, and updates to this file will (or should) be autogenerated from the source files used to build the firmware. Editing this file is therefore not recommended. i915_guc_reg.h contains definitions of GuC-related hardware: registers, bitmasks, etc. These should match the BSpec. v2: Files renamed resliced per review comments by Chris Wilson v4: Added DON'T-EDIT-ME warning [Tom O'Rourke] Issue: VIZ-4884 Signed-off-by: Alex Dai yu@intel.com Signed-off-by: Dave Gordon david.s.gor...@intel.com --- Reviewed-by: Tom O'Rourke Tom.O'rou...@intel.com Merged up to this patch, thanks. -Daniel [TOR:] Thank you. Please hold merging remaining patches in this series until guc firmware v3 is available on 01.org. Tom ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/13 v4] drm/i915: Add GuC-related header files
On Fri, Jul 17, 2015 at 05:38:05PM -0700, O'Rourke, Tom wrote: On Thu, Jul 09, 2015 at 07:29:04PM +0100, Dave Gordon wrote: intel_guc_fwif.h contains the subset of the GuC interface that we will need for submission of commands through the GuC. These MUST be kept in sync with the definitions used by the GuC firmware, and updates to this file will (or should) be autogenerated from the source files used to build the firmware. Editing this file is therefore not recommended. i915_guc_reg.h contains definitions of GuC-related hardware: registers, bitmasks, etc. These should match the BSpec. v2: Files renamed resliced per review comments by Chris Wilson v4: Added DON'T-EDIT-ME warning [Tom O'Rourke] Issue: VIZ-4884 Signed-off-by: Alex Dai yu@intel.com Signed-off-by: Dave Gordon david.s.gor...@intel.com --- Reviewed-by: Tom O'Rourke Tom.O'rou...@intel.com Merged up to this patch, thanks. -Daniel drivers/gpu/drm/i915/i915_guc_reg.h | 102 ++ drivers/gpu/drm/i915/intel_guc_fwif.h | 245 ++ 2 files changed, 347 insertions(+) create mode 100644 drivers/gpu/drm/i915/i915_guc_reg.h create mode 100644 drivers/gpu/drm/i915/intel_guc_fwif.h diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h new file mode 100644 index 000..ccdc6c8 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_guc_reg.h @@ -0,0 +1,102 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ +#ifndef _I915_GUC_REG_H_ +#define _I915_GUC_REG_H_ + +/* Definitions of GuC H/W registers, bits, etc */ + +#define GUC_STATUS 0xc000 +#define GS_BOOTROM_SHIFT 1 +#define GS_BOOTROM_MASK(0x7F GS_BOOTROM_SHIFT) +#define GS_BOOTROM_RSA_FAILED (0x50 GS_BOOTROM_SHIFT) +#define GS_UKERNEL_SHIFT 8 +#define GS_UKERNEL_MASK(0xFF GS_UKERNEL_SHIFT) +#define GS_UKERNEL_LAPIC_DONE (0x30 GS_UKERNEL_SHIFT) +#define GS_UKERNEL_DPC_ERROR (0x60 GS_UKERNEL_SHIFT) +#define GS_UKERNEL_READY (0xF0 GS_UKERNEL_SHIFT) +#define GS_MIA_SHIFT 16 +#define GS_MIA_MASK(0x07 GS_MIA_SHIFT) + +#define GUC_WOPCM_SIZE 0xc050 +#define GUC_WOPCM_SIZE_VALUE (0x80 12) /* 512KB */ +#define GUC_WOPCM_OFFSET 0x8 /* 512KB */ + +#define SOFT_SCRATCH(n)(0xc180 + ((n) * 4)) + +#define UOS_RSA_SCRATCH_0 0xc200 +#define DMA_ADDR_0_LOW 0xc300 +#define DMA_ADDR_0_HIGH0xc304 +#define DMA_ADDR_1_LOW 0xc308 +#define DMA_ADDR_1_HIGH0xc30c +#define DMA_ADDRESS_SPACE_WOPCM(7 16) +#define DMA_ADDRESS_SPACE_GTT (8 16) +#define DMA_COPY_SIZE 0xc310 +#define DMA_CTRL 0xc314 +#define UOS_MOVE (14) +#define START_DMA (10) +#define DMA_GUC_WOPCM_OFFSET 0xc340 + +#define GEN8_GT_PM_CONFIG 0x138140 +#define GEN9_GT_PM_CONFIG 0x13816c +#define GEN8_GT_DOORBELL_ENABLE(10) + +#define GEN8_GTCR 0x4274 +#define GEN8_GTCR_INVALIDATE (10) + +#define GUC_ARAT_C6DIS 0xA178 + +#define GUC_SHIM_CONTROL 0xc064 +#define GUC_DISABLE_SRAM_INIT_TO_ZEROES (10) +#define GUC_ENABLE_READ_CACHE_LOGIC (11) +#define GUC_ENABLE_MIA_CACHING (12) +#define GUC_GEN10_MSGCH_ENABLE (14) +#define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA
Re: [Intel-gfx] [PATCH 03/13 v4] drm/i915: Add GuC-related header files
On Thu, Jul 09, 2015 at 07:29:04PM +0100, Dave Gordon wrote: intel_guc_fwif.h contains the subset of the GuC interface that we will need for submission of commands through the GuC. These MUST be kept in sync with the definitions used by the GuC firmware, and updates to this file will (or should) be autogenerated from the source files used to build the firmware. Editing this file is therefore not recommended. i915_guc_reg.h contains definitions of GuC-related hardware: registers, bitmasks, etc. These should match the BSpec. v2: Files renamed resliced per review comments by Chris Wilson v4: Added DON'T-EDIT-ME warning [Tom O'Rourke] Issue: VIZ-4884 Signed-off-by: Alex Dai yu@intel.com Signed-off-by: Dave Gordon david.s.gor...@intel.com --- Reviewed-by: Tom O'Rourke Tom.O'rou...@intel.com drivers/gpu/drm/i915/i915_guc_reg.h | 102 ++ drivers/gpu/drm/i915/intel_guc_fwif.h | 245 ++ 2 files changed, 347 insertions(+) create mode 100644 drivers/gpu/drm/i915/i915_guc_reg.h create mode 100644 drivers/gpu/drm/i915/intel_guc_fwif.h diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h new file mode 100644 index 000..ccdc6c8 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_guc_reg.h @@ -0,0 +1,102 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ +#ifndef _I915_GUC_REG_H_ +#define _I915_GUC_REG_H_ + +/* Definitions of GuC H/W registers, bits, etc */ + +#define GUC_STATUS 0xc000 +#define GS_BOOTROM_SHIFT 1 +#define GS_BOOTROM_MASK (0x7F GS_BOOTROM_SHIFT) +#define GS_BOOTROM_RSA_FAILED(0x50 GS_BOOTROM_SHIFT) +#define GS_UKERNEL_SHIFT 8 +#define GS_UKERNEL_MASK (0xFF GS_UKERNEL_SHIFT) +#define GS_UKERNEL_LAPIC_DONE(0x30 GS_UKERNEL_SHIFT) +#define GS_UKERNEL_DPC_ERROR (0x60 GS_UKERNEL_SHIFT) +#define GS_UKERNEL_READY (0xF0 GS_UKERNEL_SHIFT) +#define GS_MIA_SHIFT 16 +#define GS_MIA_MASK (0x07 GS_MIA_SHIFT) + +#define GUC_WOPCM_SIZE 0xc050 +#define GUC_WOPCM_SIZE_VALUE (0x80 12) /* 512KB */ +#define GUC_WOPCM_OFFSET 0x8 /* 512KB */ + +#define SOFT_SCRATCH(n) (0xc180 + ((n) * 4)) + +#define UOS_RSA_SCRATCH_00xc200 +#define DMA_ADDR_0_LOW 0xc300 +#define DMA_ADDR_0_HIGH 0xc304 +#define DMA_ADDR_1_LOW 0xc308 +#define DMA_ADDR_1_HIGH 0xc30c +#define DMA_ADDRESS_SPACE_WOPCM (7 16) +#define DMA_ADDRESS_SPACE_GTT(8 16) +#define DMA_COPY_SIZE0xc310 +#define DMA_CTRL 0xc314 +#define UOS_MOVE (14) +#define START_DMA(10) +#define DMA_GUC_WOPCM_OFFSET 0xc340 + +#define GEN8_GT_PM_CONFIG0x138140 +#define GEN9_GT_PM_CONFIG0x13816c +#define GEN8_GT_DOORBELL_ENABLE (10) + +#define GEN8_GTCR0x4274 +#define GEN8_GTCR_INVALIDATE (10) + +#define GUC_ARAT_C6DIS 0xA178 + +#define GUC_SHIM_CONTROL 0xc064 +#define GUC_DISABLE_SRAM_INIT_TO_ZEROES(10) +#define GUC_ENABLE_READ_CACHE_LOGIC(11) +#define GUC_ENABLE_MIA_CACHING (12) +#define GUC_GEN10_MSGCH_ENABLE (14) +#define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA(19) +#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (110) +#define GUC_ENABLE_MIA_CLOCK_GATING(115) +#define GUC_GEN10_SHIM_WC_ENABLE
[Intel-gfx] [PATCH 03/13 v4] drm/i915: Add GuC-related header files
intel_guc_fwif.h contains the subset of the GuC interface that we will need for submission of commands through the GuC. These MUST be kept in sync with the definitions used by the GuC firmware, and updates to this file will (or should) be autogenerated from the source files used to build the firmware. Editing this file is therefore not recommended. i915_guc_reg.h contains definitions of GuC-related hardware: registers, bitmasks, etc. These should match the BSpec. v2: Files renamed resliced per review comments by Chris Wilson v4: Added DON'T-EDIT-ME warning [Tom O'Rourke] Issue: VIZ-4884 Signed-off-by: Alex Dai yu@intel.com Signed-off-by: Dave Gordon david.s.gor...@intel.com --- drivers/gpu/drm/i915/i915_guc_reg.h | 102 ++ drivers/gpu/drm/i915/intel_guc_fwif.h | 245 ++ 2 files changed, 347 insertions(+) create mode 100644 drivers/gpu/drm/i915/i915_guc_reg.h create mode 100644 drivers/gpu/drm/i915/intel_guc_fwif.h diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h new file mode 100644 index 000..ccdc6c8 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_guc_reg.h @@ -0,0 +1,102 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ +#ifndef _I915_GUC_REG_H_ +#define _I915_GUC_REG_H_ + +/* Definitions of GuC H/W registers, bits, etc */ + +#define GUC_STATUS 0xc000 +#define GS_BOOTROM_SHIFT 1 +#define GS_BOOTROM_MASK(0x7F GS_BOOTROM_SHIFT) +#define GS_BOOTROM_RSA_FAILED (0x50 GS_BOOTROM_SHIFT) +#define GS_UKERNEL_SHIFT 8 +#define GS_UKERNEL_MASK(0xFF GS_UKERNEL_SHIFT) +#define GS_UKERNEL_LAPIC_DONE (0x30 GS_UKERNEL_SHIFT) +#define GS_UKERNEL_DPC_ERROR (0x60 GS_UKERNEL_SHIFT) +#define GS_UKERNEL_READY (0xF0 GS_UKERNEL_SHIFT) +#define GS_MIA_SHIFT 16 +#define GS_MIA_MASK(0x07 GS_MIA_SHIFT) + +#define GUC_WOPCM_SIZE 0xc050 +#define GUC_WOPCM_SIZE_VALUE (0x80 12) /* 512KB */ +#define GUC_WOPCM_OFFSET 0x8 /* 512KB */ + +#define SOFT_SCRATCH(n)(0xc180 + ((n) * 4)) + +#define UOS_RSA_SCRATCH_0 0xc200 +#define DMA_ADDR_0_LOW 0xc300 +#define DMA_ADDR_0_HIGH0xc304 +#define DMA_ADDR_1_LOW 0xc308 +#define DMA_ADDR_1_HIGH0xc30c +#define DMA_ADDRESS_SPACE_WOPCM(7 16) +#define DMA_ADDRESS_SPACE_GTT (8 16) +#define DMA_COPY_SIZE 0xc310 +#define DMA_CTRL 0xc314 +#define UOS_MOVE (14) +#define START_DMA (10) +#define DMA_GUC_WOPCM_OFFSET 0xc340 + +#define GEN8_GT_PM_CONFIG 0x138140 +#define GEN9_GT_PM_CONFIG 0x13816c +#define GEN8_GT_DOORBELL_ENABLE(10) + +#define GEN8_GTCR 0x4274 +#define GEN8_GTCR_INVALIDATE (10) + +#define GUC_ARAT_C6DIS 0xA178 + +#define GUC_SHIM_CONTROL 0xc064 +#define GUC_DISABLE_SRAM_INIT_TO_ZEROES (10) +#define GUC_ENABLE_READ_CACHE_LOGIC (11) +#define GUC_ENABLE_MIA_CACHING (12) +#define GUC_GEN10_MSGCH_ENABLE (14) +#define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA (19) +#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (110) +#define GUC_ENABLE_MIA_CLOCK_GATING (115) +#define GUC_GEN10_SHIM_WC_ENABLE (121) + +#define GUC_SHIM_CONTROL_VALUE (GUC_DISABLE_SRAM_INIT_TO_ZEROES| \ +GUC_ENABLE_READ_CACHE_LOGIC| \ +GUC_ENABLE_MIA_CACHING | \ +
