[Intel-gfx] [PATCH 03/20] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake

[José Roberto de Souza]

Instead of have the same code spread into 4 platforms lets share it.

Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e209edbc561d..9575b7402172 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3264,18 +3264,24 @@ static void icl_mbus_init(struct drm_i915_private 
*dev_priv)
        I915_WRITE(MBUS_ABOX_CTL, val);
 }
 
+static void skl_pch_reset_handshake(struct drm_i915_private *dev_priv)
+{
+       u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
+
+       val |= RESET_PCH_HANDSHAKE_ENABLE;
+       I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+}
+
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
                                   bool resume)
 {
        struct i915_power_domains *power_domains = &dev_priv->power_domains;
        struct i915_power_well *well;
-       uint32_t val;
 
        gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
        /* enable PCH reset handshake */
-       val = I915_READ(HSW_NDE_RSTWRN_OPT);
-       I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
+       skl_pch_reset_handshake(dev_priv);
 
        /* enable PG1 and Misc I/O */
        mutex_lock(&power_domains->lock);
@@ -3331,7 +3337,6 @@ void bxt_display_core_init(struct drm_i915_private 
*dev_priv,
 {
        struct i915_power_domains *power_domains = &dev_priv->power_domains;
        struct i915_power_well *well;
-       uint32_t val;
 
        gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
@@ -3341,9 +3346,7 @@ void bxt_display_core_init(struct drm_i915_private 
*dev_priv,
         * Move the handshake programming to initialization sequence.
         * Previously was left up to BIOS.
         */
-       val = I915_READ(HSW_NDE_RSTWRN_OPT);
-       val &= ~RESET_PCH_HANDSHAKE_ENABLE;
-       I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+       skl_pch_reset_handshake(dev_priv);
 
        /* Enable PG1 */
        mutex_lock(&power_domains->lock);
@@ -3464,9 +3467,7 @@ static void cnl_display_core_init(struct drm_i915_private 
*dev_priv, bool resume
        gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
        /* 1. Enable PCH Reset Handshake */
-       val = I915_READ(HSW_NDE_RSTWRN_OPT);
-       val |= RESET_PCH_HANDSHAKE_ENABLE;
-       I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+       skl_pch_reset_handshake(dev_priv);
 
        /* 2. Enable Comp */
        val = I915_READ(CHICKEN_MISC_2);
@@ -3549,9 +3550,7 @@ static void icl_display_core_init(struct drm_i915_private 
*dev_priv,
        gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
        /* 1. Enable PCH reset handshake. */
-       val = I915_READ(HSW_NDE_RSTWRN_OPT);
-       val |= RESET_PCH_HANDSHAKE_ENABLE;
-       I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+       skl_pch_reset_handshake(dev_priv);
 
        for (port = PORT_A; port <= PORT_B; port++) {
                /* 2. Enable DDI combo PHY comp. */
-- 
2.18.0

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