[Intel-gfx] [PATCH 04/14] drm/i915: Enable PCH FIFO underruns later on HSW+

[ville . syrjala]

From: Ville Syrjälä 

As we did for ILK/SNB/IVB, move the PCH FIFO underrun enable to happen
after the encoder enable on HSW+. And again, for symmetry, move the
the disable to happen before encoder disable.

I've left out the vblank wait before the enable here because I don't
know if it's needed or not. Actually I don't know if this entire
change is needed as I don't have a HSW/BDW with VGA output.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index d5cb899..4fc3d24 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4971,11 +4971,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
encoder->pre_enable(encoder);
}
 
-   if (intel_crtc->config->has_pch_encoder) {
-   intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
- true);
+   if (intel_crtc->config->has_pch_encoder)
dev_priv->display.fdi_link_train(crtc);
-   }
 
if (!is_dsi)
intel_ddi_enable_pipe_clock(intel_crtc);
@@ -5012,6 +5009,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_opregion_notify_encoder(encoder, true);
}
 
+   if (intel_crtc->config->has_pch_encoder)
+   intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
+ true);
+
/* If we change the relative order between pipe/planes enabling, we need
 * to change the workaround. */
hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
@@ -5096,6 +5097,10 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
 
+   if (intel_crtc->config->has_pch_encoder)
+   intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
+ false);
+
for_each_encoder_on_crtc(dev, crtc, encoder) {
intel_opregion_notify_encoder(encoder, false);
encoder->disable(encoder);
@@ -5104,9 +5109,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
 
-   if (intel_crtc->config->has_pch_encoder)
-   intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
- false);
intel_disable_pipe(intel_crtc);
 
if (intel_crtc->config->dp_encoder_is_mst)
-- 
2.4.10

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Re: [Intel-gfx] [PATCH 04/14] drm/i915: Enable PCH FIFO underruns later on HSW+

[Jesse Barnes]

On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> As we did for ILK/SNB/IVB, move the PCH FIFO underrun enable to happen
> after the encoder enable on HSW+. And again, for symmetry, move the
> the disable to happen before encoder disable.
> 
> I've left out the vblank wait before the enable here because I don't
> know if it's needed or not. Actually I don't know if this entire
> change is needed as I don't have a HSW/BDW with VGA output.
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 16 +---
>  1 file changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index d5cb899..4fc3d24 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4971,11 +4971,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>   encoder->pre_enable(encoder);
>   }
>  
> - if (intel_crtc->config->has_pch_encoder) {
> - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> -   true);
> + if (intel_crtc->config->has_pch_encoder)
>   dev_priv->display.fdi_link_train(crtc);
> - }
>  
>   if (!is_dsi)
>   intel_ddi_enable_pipe_clock(intel_crtc);
> @@ -5012,6 +5009,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>   intel_opregion_notify_encoder(encoder, true);
>   }
>  
> + if (intel_crtc->config->has_pch_encoder)
> + intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> +   true);
> +
>   /* If we change the relative order between pipe/planes enabling, we need
>* to change the workaround. */
>   hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
> @@ -5096,6 +5097,10 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>   enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>   bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>  
> + if (intel_crtc->config->has_pch_encoder)
> + intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> +   false);
> +
>   for_each_encoder_on_crtc(dev, crtc, encoder) {
>   intel_opregion_notify_encoder(encoder, false);
>   encoder->disable(encoder);
> @@ -5104,9 +5109,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>   drm_crtc_vblank_off(crtc);
>   assert_vblank_disabled(crtc);
>  
> - if (intel_crtc->config->has_pch_encoder)
> - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> -   false);
>   intel_disable_pipe(intel_crtc);
>  
>   if (intel_crtc->config->dp_encoder_is_mst)
> 

Reviewed-by: Jesse Barnes 
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