Re: [Intel-gfx] [PATCH 05/17] drm/i915/icl: compute the MG PLL registers

[Manasi Navare]

On Thu, Feb 22, 2018 at 12:55:07AM -0300, Paulo Zanoni wrote:
> This implements the "MG PLL Programming" sequence from our spec. The
> biggest problem was that the spec assumes real numbers, so we had to
> adjust some numbers and alculations due to the fact that the Kernel
> prefers to deal with integers.
> 
> I recommend grabbing some coffee, a pen and paper before reviewing
> this patch.
> 
> v2:
>  - Correctly identify DP encoders after upstream change.
>  - Small checkpatch issues.
>  - Rebase.
> 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 217 
> +-
>  1 file changed, 216 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 5d7bacc80688..9a2965e0b883 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2514,11 +2514,226 @@ static enum intel_dpll_id icl_port_to_mg_pll_id(enum 
> port port)
>   return port - PORT_C + DPLL_ID_ICL_MGPLL1;
>  }
>  
> +static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
> +  uint32_t *target_dco_khz,
> +  struct intel_dpll_hw_state *state)
> +{
> + uint32_t dco_min_freq, dco_max_freq;
> + int div1_vals[] = {7, 5, 3, 2};
> + unsigned int i;
> + int div2;
> +
> + dco_min_freq = is_dp ? 810 : use_ssc ? 800 : 7992000;
> + dco_max_freq = is_dp ? 810 : 1000;
> +
> + for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
> + int div1 = div1_vals[i];
> +
> + for (div2 = 10; div2 > 0; div2--) {
> + int dco = div1 * div2 * clock_khz * 5;
> + int a_divratio, tlinedrv, inputsel, hsdiv;
> +
> + if (dco < dco_min_freq || dco > dco_max_freq)
> + continue;
> +
> + if (div2 >= 2) {
> + a_divratio = is_dp ? 10 : 5;
> + tlinedrv = 2;
> + } else {
> + a_divratio = 5;
> + tlinedrv = 0;
> + }
> + inputsel = is_dp ? 0 : 1;
> +
> + switch (div1) {
> + default:
> + MISSING_CASE(div1);
> + case 2:
> + hsdiv = 0;
> + break;
> + case 3:
> + hsdiv = 1;
> + break;
> + case 5:
> + hsdiv = 2;
> + break;
> + case 7:
> + hsdiv = 3;
> + break;
> + }
> +
> + *target_dco_khz = dco;
> +
> + state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
> +
> + state->mg_clktop2_coreclkctl1 =
> + MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
> +
> + state->mg_clktop2_hsclkctl =
> + MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
> + MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
> + MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(hsdiv) |
> + MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
> +
> + return true;
> + }
> + }
> +
> + return false;
> +}
> +
> +/*
> + * The specification for this function uses real numbers, so the math had to 
> be
> + * adapted to integer-only calculation, that's why it looks so different.
> + */
>  static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder, int clock,
> struct intel_dpll_hw_state *pll_state)
>  {
> - /* TODO */
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + int refclk_khz = dev_priv->cdclk.hw.ref;
> + uint32_t dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
> + uint32_t iref_ndiv, iref_trim, iref_pulse_w;
> + uint32_t prop_coeff, int_coeff;
> + uint32_t tdc_targetcnt, feedfwgain;
> + uint64_t ssc_stepsize, ssc_steplen, ssc_steplog;
> + uint64_t tmp;
> + bool use_ssc = false;
> + bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
> +
> + if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, _khz,
> +   pll_state)) {
> + DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
> + return false;
> + }
> +
> + m1div = 2;
> + m2div_int = dco_khz / (refclk_khz * m1div);
> + if (m2div_int > 255) {
> + m1div = 4;
> + 

[Intel-gfx] [PATCH 05/17] drm/i915/icl: compute the MG PLL registers

[Paulo Zanoni]

This implements the "MG PLL Programming" sequence from our spec. The
biggest problem was that the spec assumes real numbers, so we had to
adjust some numbers and alculations due to the fact that the Kernel
prefers to deal with integers.

I recommend grabbing some coffee, a pen and paper before reviewing
this patch.

v2:
 - Correctly identify DP encoders after upstream change.
 - Small checkpatch issues.
 - Rebase.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 217 +-
 1 file changed, 216 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 5d7bacc80688..9a2965e0b883 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2514,11 +2514,226 @@ static enum intel_dpll_id icl_port_to_mg_pll_id(enum 
port port)
return port - PORT_C + DPLL_ID_ICL_MGPLL1;
 }
 
+static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
+uint32_t *target_dco_khz,
+struct intel_dpll_hw_state *state)
+{
+   uint32_t dco_min_freq, dco_max_freq;
+   int div1_vals[] = {7, 5, 3, 2};
+   unsigned int i;
+   int div2;
+
+   dco_min_freq = is_dp ? 810 : use_ssc ? 800 : 7992000;
+   dco_max_freq = is_dp ? 810 : 1000;
+
+   for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
+   int div1 = div1_vals[i];
+
+   for (div2 = 10; div2 > 0; div2--) {
+   int dco = div1 * div2 * clock_khz * 5;
+   int a_divratio, tlinedrv, inputsel, hsdiv;
+
+   if (dco < dco_min_freq || dco > dco_max_freq)
+   continue;
+
+   if (div2 >= 2) {
+   a_divratio = is_dp ? 10 : 5;
+   tlinedrv = 2;
+   } else {
+   a_divratio = 5;
+   tlinedrv = 0;
+   }
+   inputsel = is_dp ? 0 : 1;
+
+   switch (div1) {
+   default:
+   MISSING_CASE(div1);
+   case 2:
+   hsdiv = 0;
+   break;
+   case 3:
+   hsdiv = 1;
+   break;
+   case 5:
+   hsdiv = 2;
+   break;
+   case 7:
+   hsdiv = 3;
+   break;
+   }
+
+   *target_dco_khz = dco;
+
+   state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
+
+   state->mg_clktop2_coreclkctl1 =
+   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
+
+   state->mg_clktop2_hsclkctl =
+   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
+   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
+   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(hsdiv) |
+   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
+
+   return true;
+   }
+   }
+
+   return false;
+}
+
+/*
+ * The specification for this function uses real numbers, so the math had to be
+ * adapted to integer-only calculation, that's why it looks so different.
+ */
 static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
  struct intel_encoder *encoder, int clock,
  struct intel_dpll_hw_state *pll_state)
 {
-   /* TODO */
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   int refclk_khz = dev_priv->cdclk.hw.ref;
+   uint32_t dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
+   uint32_t iref_ndiv, iref_trim, iref_pulse_w;
+   uint32_t prop_coeff, int_coeff;
+   uint32_t tdc_targetcnt, feedfwgain;
+   uint64_t ssc_stepsize, ssc_steplen, ssc_steplog;
+   uint64_t tmp;
+   bool use_ssc = false;
+   bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
+
+   if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, _khz,
+ pll_state)) {
+   DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
+   return false;
+   }
+
+   m1div = 2;
+   m2div_int = dco_khz / (refclk_khz * m1div);
+   if (m2div_int > 255) {
+   m1div = 4;
+   m2div_int = dco_khz / (refclk_khz * m1div);
+   if (m2div_int > 255) {
+   DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n",
+