Re: [Intel-gfx] [PATCH 07/18] drm/i915/display13: Add Display13 power wells
On Thu, Jan 28, 2021 at 11:24:02AM -0800, Matt Roper wrote:
Aside from the hardware-managed PG0, Display13 has power wells 1-2 and
A-D. These power wells should be enabled/disabled according to the
following dependency tree (enable top to bottom, disable bottom to top):
PG0
|
--PG1--
/ \
PGA --PG2--
/ | \
PGB PGC PGD
PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the
bits that would have been PG 6-9 under the old scheme.
PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same
as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
Bspec: 49233
Bspec: 49503
Bspec: 49504
Bspec: 49505
Bspec: 49296
Bspec: 50090
Bspec: 53920
Cc: Anshuman Gupta
Cc: Imre Deak
Cc: Anshuman Gupta
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.c| 422 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +-
drivers/gpu/drm/i915/i915_reg.h | 10 +
3 files changed, 433 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e17b1ca356c3..7dd12fe9137e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1035,7 +1035,7 @@ static void assert_can_enable_dc5(struct drm_i915_private
*dev_priv)
enum i915_power_well_id high_pg;
/* Power wells at this level and above must be disabled for DC5 entry */
- if (INTEL_GEN(dev_priv) >= 12)
+ if (INTEL_GEN(dev_priv) >= 12 && !HAS_DISPLAY13(dev_priv))
high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
@@ -3028,6 +3028,109 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
+/*
+ * Display13 Power Domains
+ *
+ * Previous platforms required that PG(n-1) be enabled before PG(n). That
+ * dependency chain turns into a dependency tree on Display13:
+ *
+ * PG0
+ *|
+ * --PG1--
+ */ \
+ * PGA --PG2--
+ * / | \
+ * PGB PGC PGD
+ *
+ * Power wells must be enabled from top to bottom and disabled from bottom
+ * to top. This allows pipes to be power gated independently.
+ */
+
+#define D13_PW_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
when reviewing this in the spec I thought this was wrong... apparently
transcoder_{b,c,d} power wells
are in PG2, but there is a clarification in bspec 49233:
"Transcoder B (registers reside in PG2, but access path goes through
associated pipe)"
Reviewed-by: Lucas De Marchi
Lucas De Marchi
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_2_POWER_DOMAINS ( \
+ D13_PW_B_POWER_DOMAINS |\
+ D13_PW_C_POWER_DOMAINS |\
+ D13_PW_D_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_G_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_H_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_I_LANES) |\
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_AUX_G) | \
+ BIT_ULL(POWER_DOMAIN_AUX_H) | \
+ BIT_ULL(POWER_DOMAIN_AUX_I) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * D13
[Intel-gfx] [PATCH 07/18] drm/i915/display13: Add Display13 power wells
Aside from the hardware-managed PG0, Display13 has power wells 1-2 and
A-D. These power wells should be enabled/disabled according to the
following dependency tree (enable top to bottom, disable bottom to top):
PG0
|
--PG1--
/ \
PGA --PG2--
/ | \
PGB PGC PGD
PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the
bits that would have been PG 6-9 under the old scheme.
PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same
as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
Bspec: 49233
Bspec: 49503
Bspec: 49504
Bspec: 49505
Bspec: 49296
Bspec: 50090
Bspec: 53920
Cc: Anshuman Gupta
Cc: Imre Deak
Cc: Anshuman Gupta
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.c| 422 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +-
drivers/gpu/drm/i915/i915_reg.h | 10 +
3 files changed, 433 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e17b1ca356c3..7dd12fe9137e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1035,7 +1035,7 @@ static void assert_can_enable_dc5(struct drm_i915_private
*dev_priv)
enum i915_power_well_id high_pg;
/* Power wells at this level and above must be disabled for DC5 entry */
- if (INTEL_GEN(dev_priv) >= 12)
+ if (INTEL_GEN(dev_priv) >= 12 && !HAS_DISPLAY13(dev_priv))
high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
@@ -3028,6 +3028,109 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
+/*
+ * Display13 Power Domains
+ *
+ * Previous platforms required that PG(n-1) be enabled before PG(n). That
+ * dependency chain turns into a dependency tree on Display13:
+ *
+ * PG0
+ *|
+ * --PG1--
+ */ \
+ * PGA --PG2--
+ * / | \
+ * PGB PGC PGD
+ *
+ * Power wells must be enabled from top to bottom and disabled from bottom
+ * to top. This allows pipes to be power gated independently.
+ */
+
+#define D13_PW_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_2_POWER_DOMAINS ( \
+ D13_PW_B_POWER_DOMAINS |\
+ D13_PW_C_POWER_DOMAINS |\
+ D13_PW_D_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_G_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_H_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_I_LANES) |\
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_AUX_G) | \
+ BIT_ULL(POWER_DOMAIN_AUX_H) | \
+ BIT_ULL(POWER_DOMAIN_AUX_I) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * D13 PW_1/PG_1 domains (under HW/DMC control):
+ * - DBUF function (registers are in PW0)
+ * - Transcoder A
+ * - DDI_A and DDI_B
+ *
+ * D13 PW_0/PW_1 domains (under HW/DMC control):
+ * - PCI
+ * - Clocks except port PLL
+ * - Shared functions:
+ * * interrupts except pipe interrupts
+ * * MBus except PIPE_MBUS_DBOX_CTL
+ * * DBUF registers
