Prepared substructure rps for RPS related state. autoenable_work and
pcu_lock are used for RC6 hence they are defined outside rps structure.
Renamed the RPS lock as pcu_lock.
Cc: Chris Wilson
Cc: Imre Deak
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c| 117 +-
drivers/gpu/drm/i915/i915_drv.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 12 +-
drivers/gpu/drm/i915/i915_gem_request.c| 2 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 8 +-
drivers/gpu/drm/i915/i915_irq.c| 86 +++
drivers/gpu/drm/i915/i915_sysfs.c | 70 +++---
drivers/gpu/drm/i915/intel_cdclk.c | 40 ++--
drivers/gpu/drm/i915/intel_display.c | 12 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c| 363 +++--
drivers/gpu/drm/i915/intel_runtime_pm.c| 16 +-
drivers/gpu/drm/i915/intel_sideband.c | 6 +-
13 files changed, 379 insertions(+), 357 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8126c2c..9356a69 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1026,6 +1026,7 @@ static int i915_error_state_open(struct inode *inode,
struct file *file)
static int i915_frequency_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_rps *rps = &dev_priv->pm.rps;
int ret = 0;
intel_runtime_pm_get(dev_priv);
@@ -1043,7 +1044,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
u32 freq_sts;
- mutex_lock(&dev_priv->rps.hw_lock);
+ mutex_lock(&dev_priv->pm.pcu_lock);
freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
@@ -1052,21 +1053,21 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
seq_printf(m, "current GPU freq: %d MHz\n",
- intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+ intel_gpu_freq(dev_priv, rps->cur_freq));
seq_printf(m, "max GPU freq: %d MHz\n",
- intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
+ intel_gpu_freq(dev_priv, rps->max_freq));
seq_printf(m, "min GPU freq: %d MHz\n",
- intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
+ intel_gpu_freq(dev_priv, rps->min_freq));
seq_printf(m, "idle GPU freq: %d MHz\n",
- intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
+ intel_gpu_freq(dev_priv, rps->idle_freq));
seq_printf(m,
"efficient (RPe) frequency: %d MHz\n",
- intel_gpu_freq(dev_priv,
dev_priv->rps.efficient_freq));
- mutex_unlock(&dev_priv->rps.hw_lock);
+ intel_gpu_freq(dev_priv, rps->efficient_freq));
+ mutex_unlock(&dev_priv->pm.pcu_lock);
} else if (INTEL_GEN(dev_priv) >= 6) {
u32 rp_state_limits;
u32 gt_perf_status;
@@ -1146,7 +1147,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x,
MASK=0x%08x\n",
pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
- dev_priv->rps.pm_intrmsk_mbz);
+ rps->pm_intrmsk_mbz);
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
seq_printf(m, "Render p-state ratio: %d\n",
(gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ?
0x1ff00 : 0xff00)) >> 8);
@@ -1166,8 +1167,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
seq_printf(m, "RP PREV UP: %d (%dus)\n",
rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
- seq_printf(m, "Up threshold: %d%%\n",
- dev_priv->rps.up_threshold);
+ seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
@@ -1175,8 +1175,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
rpcurdo
