Re: [Intel-gfx] [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions)

2021-07-02 Thread Tvrtko Ursulin 



On 01/07/2021 21:23, Matt Roper wrote:

From: John Harrison 

Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.

Cc: Tvrtko Ursulin 
Signed-off-by: John Harrison 
Signed-off-by: Tomas Winkler 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c |  7 ++-
  drivers/gpu/drm/i915/gt/intel_engine_cs.c| 50 
  drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 --
  drivers/gpu/drm/i915/i915_reg.h  |  6 +++
  4 files changed, 69 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 87b06572fd2e..35edc55720f4 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -279,7 +279,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE)
aux_inv = rq->engine->mask & ~BIT(BCS0);
if (aux_inv)
-   cmd += 2 * hweight8(aux_inv) + 2;
+   cmd += 2 * hweight32(aux_inv) + 2;
  
  	cs = intel_ring_begin(rq, cmd);

if (IS_ERR(cs))
@@ -313,9 +313,8 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
struct intel_engine_cs *engine;
unsigned int tmp;
  
-		*cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));

-   for_each_engine_masked(engine, rq->engine->gt,
-  aux_inv, tmp) {
+   *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));
+   for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {
*cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
*cs++ = AUX_INV;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 4ab2c9abb943..6e2aa1acc4d4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -104,6 +104,38 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
},
},
+   [VCS4] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_DECODE_CLASS,
+   .instance = 4,
+   .mmio_bases = {
+   { .graphics_ver = 11, .base = XEHP_BSD5_RING_BASE }
+   },
+   },
+   [VCS5] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_DECODE_CLASS,
+   .instance = 5,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }
+   },
+   },
+   [VCS6] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_DECODE_CLASS,
+   .instance = 6,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }
+   },
+   },
+   [VCS7] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_DECODE_CLASS,
+   .instance = 7,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }
+   },
+   },
[VECS0] = {
.hw_id = VECS0_HW,
.class = VIDEO_ENHANCEMENT_CLASS,
@@ -121,6 +153,22 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
},
},
+   [VECS2] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_ENHANCEMENT_CLASS,
+   .instance = 2,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }
+   },
+   },
+   [VECS3] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_ENHANCEMENT_CLASS,
+   .instance = 3,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
+   },
+   },
  };
  
  /**

@@ -269,6 +317,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum 
intel_engine_id id)
  
  	BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));

BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
+   BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));
+   BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));
  
  	if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))

return -EINVAL;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 5b91068ab277..b25f594a7e4b 100644
--- a/driver

[Intel-gfx] [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions)

2021-07-01 Thread Matt Roper 
From: John Harrison 

Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.

Cc: Tvrtko Ursulin 
Signed-off-by: John Harrison 
Signed-off-by: Tomas Winkler 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c |  7 ++-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c| 50 
 drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 --
 drivers/gpu/drm/i915/i915_reg.h  |  6 +++
 4 files changed, 69 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 87b06572fd2e..35edc55720f4 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -279,7 +279,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE)
aux_inv = rq->engine->mask & ~BIT(BCS0);
if (aux_inv)
-   cmd += 2 * hweight8(aux_inv) + 2;
+   cmd += 2 * hweight32(aux_inv) + 2;
 
cs = intel_ring_begin(rq, cmd);
if (IS_ERR(cs))
@@ -313,9 +313,8 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
struct intel_engine_cs *engine;
unsigned int tmp;
 
-   *cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));
-   for_each_engine_masked(engine, rq->engine->gt,
-  aux_inv, tmp) {
+   *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));
+   for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {
*cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
*cs++ = AUX_INV;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 4ab2c9abb943..6e2aa1acc4d4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -104,6 +104,38 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
},
},
+   [VCS4] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_DECODE_CLASS,
+   .instance = 4,
+   .mmio_bases = {
+   { .graphics_ver = 11, .base = XEHP_BSD5_RING_BASE }
+   },
+   },
+   [VCS5] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_DECODE_CLASS,
+   .instance = 5,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }
+   },
+   },
+   [VCS6] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_DECODE_CLASS,
+   .instance = 6,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }
+   },
+   },
+   [VCS7] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_DECODE_CLASS,
+   .instance = 7,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }
+   },
+   },
[VECS0] = {
.hw_id = VECS0_HW,
.class = VIDEO_ENHANCEMENT_CLASS,
@@ -121,6 +153,22 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
},
},
+   [VECS2] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_ENHANCEMENT_CLASS,
+   .instance = 2,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }
+   },
+   },
+   [VECS3] = {
+   .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
+   .class = VIDEO_ENHANCEMENT_CLASS,
+   .instance = 3,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
+   },
+   },
 };
 
 /**
@@ -269,6 +317,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum 
intel_engine_id id)
 
BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
+   BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));
+   BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));
 
if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 5b91068ab277..b25f594a7e4b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_t