Re: [Intel-gfx] [PATCH 1/2] drm/i915/hdcp: split out hdcp registers to a separate file

2022-08-09 Thread Murthy, Arun R
> -Original Message-
> From: Intel-gfx  On Behalf Of Jani
> Nikula
> Sent: Thursday, August 4, 2022 3:29 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani 
> Subject: [Intel-gfx] [PATCH 1/2] drm/i915/hdcp: split out hdcp registers to a
> separate file
> 
> Reduce the bloat of i915_reg.h. The registers are also only needed in a few
> places, no need to have them defined everywhere.
> 
> Signed-off-by: Jani Nikula 
> ---


Reviewed-by: Arun R Murthy 

Thanks and Regards,
Arun R Murthy



[Intel-gfx] [PATCH 1/2] drm/i915/hdcp: split out hdcp registers to a separate file

2022-08-04 Thread Jani Nikula
Reduce the bloat of i915_reg.h. The registers are also only needed in a
few places, no need to have them defined everywhere.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dp_hdcp.c  |   1 +
 drivers/gpu/drm/i915/display/intel_hdcp.c |   1 +
 .../gpu/drm/i915/display/intel_hdcp_regs.h| 270 ++
 drivers/gpu/drm/i915/display/intel_hdmi.c |   1 +
 drivers/gpu/drm/i915/i915_reg.h   | 259 -
 5 files changed, 273 insertions(+), 259 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c 
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index a7640dbcf00e..88689124c013 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -17,6 +17,7 @@
 #include "intel_dp.h"
 #include "intel_dp_hdcp.h"
 #include "intel_hdcp.h"
+#include "intel_hdcp_regs.h"
 
 static unsigned int transcoder_to_stream_enc_status(enum transcoder 
cpu_transcoder)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c 
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 8ea66a2e1b09..c5e9e86bb4cb 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -23,6 +23,7 @@
 #include "intel_display_power_well.h"
 #include "intel_display_types.h"
 #include "intel_hdcp.h"
+#include "intel_hdcp_regs.h"
 #include "intel_pcode.h"
 
 #define KEY_LOAD_TRIES 5
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_regs.h 
b/drivers/gpu/drm/i915/display/intel_hdcp_regs.h
new file mode 100644
index ..cbeab64e69d2
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_regs.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_HDCP_REGS_H__
+#define __INTEL_HDCP_REGS_H__
+
+#include "i915_reg_defs.h"
+
+/* HDCP Key Registers */
+#define HDCP_KEY_CONF  _MMIO(0x66c00)
+#define  HDCP_AKSV_SEND_TRIGGERBIT(31)
+#define  HDCP_CLEAR_KEYS_TRIGGER   BIT(30)
+#define  HDCP_KEY_LOAD_TRIGGER BIT(8)
+#define HDCP_KEY_STATUS_MMIO(0x66c04)
+#define  HDCP_FUSE_IN_PROGRESS BIT(7)
+#define  HDCP_FUSE_ERROR   BIT(6)
+#define  HDCP_FUSE_DONEBIT(5)
+#define  HDCP_KEY_LOAD_STATUS  BIT(1)
+#define  HDCP_KEY_LOAD_DONEBIT(0)
+#define HDCP_AKSV_LO   _MMIO(0x66c10)
+#define HDCP_AKSV_HI   _MMIO(0x66c14)
+
+/* HDCP Repeater Registers */
+#define HDCP_REP_CTL   _MMIO(0x66d00)
+#define  HDCP_TRANSA_REP_PRESENT   BIT(31)
+#define  HDCP_TRANSB_REP_PRESENT   BIT(30)
+#define  HDCP_TRANSC_REP_PRESENT   BIT(29)
+#define  HDCP_TRANSD_REP_PRESENT   BIT(28)
+#define  HDCP_DDIB_REP_PRESENT BIT(30)
+#define  HDCP_DDIA_REP_PRESENT BIT(29)
+#define  HDCP_DDIC_REP_PRESENT BIT(28)
+#define  HDCP_DDID_REP_PRESENT BIT(27)
+#define  HDCP_DDIF_REP_PRESENT BIT(26)
+#define  HDCP_DDIE_REP_PRESENT BIT(25)
+#define  HDCP_TRANSA_SHA1_M0   (1 << 20)
+#define  HDCP_TRANSB_SHA1_M0   (2 << 20)
+#define  HDCP_TRANSC_SHA1_M0   (3 << 20)
+#define  HDCP_TRANSD_SHA1_M0   (4 << 20)
+#define  HDCP_DDIB_SHA1_M0 (1 << 20)
+#define  HDCP_DDIA_SHA1_M0 (2 << 20)
+#define  HDCP_DDIC_SHA1_M0 (3 << 20)
+#define  HDCP_DDID_SHA1_M0 (4 << 20)
+#define  HDCP_DDIF_SHA1_M0 (5 << 20)
+#define  HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
+#define  HDCP_SHA1_BUSYBIT(16)
+#define  HDCP_SHA1_READY   BIT(17)
+#define  HDCP_SHA1_COMPLETEBIT(18)
+#define  HDCP_SHA1_V_MATCH BIT(19)
+#define  HDCP_SHA1_TEXT_32 (1 << 1)
+#define  HDCP_SHA1_COMPLETE_HASH   (2 << 1)
+#define  HDCP_SHA1_TEXT_24 (4 << 1)
+#define  HDCP_SHA1_TEXT_16 (5 << 1)
+#define  HDCP_SHA1_TEXT_8  (6 << 1)
+#define  HDCP_SHA1_TEXT_0  (7 << 1)
+#define HDCP_SHA_V_PRIME_H0_MMIO(0x66d04)
+#define HDCP_SHA_V_PRIME_H1_MMIO(0x66d08)
+#define HDCP_SHA_V_PRIME_H2_MMIO(0x66d0C)
+#define HDCP_SHA_V_PRIME_H3_MMIO(0x66d10)
+#define HDCP_SHA_V_PRIME_H4_MMIO(0x66d14)
+#define HDCP_SHA_V_PRIME(h)_MMIO((0x66d04 + (h) * 4))
+#define HDCP_SHA_TEXT  _MMIO(0x66d18)
+
+/* HDCP Auth Registers */
+#define _PORTA_HDCP_AUTHENC0x66800
+#define _PORTB_HDCP_AUTHENC0x66500
+#define _PORTC_HDCP_AUTHENC0x66600
+#define _PORTD_HDCP_AUTHENC0x66700
+#define _PORTE_HDCP_AUTHENC0x66A00
+#define _PORTF_HDCP_AUTHENC0x66900
+#define _PORT_HDCP_AUTHENC(port, x)_MMIO(_PICK(port, \
+ _PORTA_HDCP_AUTHENC, \
+