Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix fast wake AUX sync len

2023-03-30 Thread Hogander, Jouni
On Wed, 2023-03-29 at 20:24 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Fast wake should use 8 SYNC pulses for the preamble
> and 10-16 SYNC pulses for the precharge. Recuce our
> fast wake SYNC count to match the maximum value.
> We also use the maximum precharge length for normal
> AUX transactions.
> 
> Cc: Jouni Högander 
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jouni Högander 

> ---
>  drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index eb07dc5d8709..ad0aac707219 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -164,7 +164,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp
> *intel_dp,
>   DP_AUX_CH_CTL_TIME_OUT_MAX |
>   DP_AUX_CH_CTL_RECEIVE_ERROR |
>   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> - DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
> + DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(24) |
>   DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
>  
> if (intel_tc_port_in_tbt_alt_mode(dig_port))



[Intel-gfx] [PATCH 1/2] drm/i915: Fix fast wake AUX sync len

2023-03-29 Thread Ville Syrjala
From: Ville Syrjälä 

Fast wake should use 8 SYNC pulses for the preamble
and 10-16 SYNC pulses for the precharge. Recuce our
fast wake SYNC count to match the maximum value.
We also use the maximum precharge length for normal
AUX transactions.

Cc: Jouni Högander 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index eb07dc5d8709..ad0aac707219 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -164,7 +164,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
  DP_AUX_CH_CTL_TIME_OUT_MAX |
  DP_AUX_CH_CTL_RECEIVE_ERROR |
  (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
+ DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(24) |
  DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 
if (intel_tc_port_in_tbt_alt_mode(dig_port))
-- 
2.39.2