Re: [Intel-gfx] [PATCH 1/2] drm/i915: Set M2_N2 registers during mode set
On Jul-10-2014 2:42 AM, Jesse Barnes wrote:
> On Mon, 7 Jul 2014 14:59:45 +0530
> Vandana Kannan wrote:
>
>> For Gen < 8, set M2_N2 registers on every mode set. This is required to make
>> sure M2_N2 registers are set during boot, resume from sleep for cross-
>> checking the state. The register is set only if DRRS is supported.
>>
>> v2: Patch rebased
>>
>> v3: Daniel's review comments
>> - Removed HAS_DRRS(dev) and added bool has_drrs to pipe_config to
>> track drrs support
>>
>> Signed-off-by: Vandana Kannan
>> Cc: Daniel Vetter
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 36
>>
>> drivers/gpu/drm/i915/intel_dp.c | 16 ++--
>> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>> 3 files changed, 36 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index a72b55f..22bdea5f 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4020,8 +4020,12 @@ static void ironlake_crtc_enable(struct drm_crtc
>> *crtc)
>> if (intel_crtc->config.has_pch_encoder)
>> intel_prepare_shared_dpll(intel_crtc);
>>
>> -if (intel_crtc->config.has_dp_encoder)
>> +if (intel_crtc->config.has_dp_encoder) {
>> intel_dp_set_m_n(intel_crtc);
>> +if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
>> +intel_dp_set_m2_n2(intel_crtc,
>> +&intel_crtc->config.dp_m2_n2);
>> +}
>>
>> intel_set_pipe_timings(intel_crtc);
>>
>> @@ -4130,8 +4134,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>> if (intel_crtc->active)
>> return;
>>
>> -if (intel_crtc->config.has_dp_encoder)
>> +if (intel_crtc->config.has_dp_encoder) {
>> intel_dp_set_m_n(intel_crtc);
>> +if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
>> +intel_dp_set_m2_n2(intel_crtc,
>> +&intel_crtc->config.dp_m2_n2);
>> +}
>>
>> intel_set_pipe_timings(intel_crtc);
>>
>> @@ -4648,8 +4656,12 @@ static void valleyview_crtc_enable(struct drm_crtc
>> *crtc)
>> /* Set up the display plane register */
>> dspcntr = DISPPLANE_GAMMA_ENABLE;
>>
>> -if (intel_crtc->config.has_dp_encoder)
>> +if (intel_crtc->config.has_dp_encoder) {
>> intel_dp_set_m_n(intel_crtc);
>> +if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
>> +intel_dp_set_m2_n2(intel_crtc,
>> +&intel_crtc->config.dp_m2_n2);
>> +}
>>
>> intel_set_pipe_timings(intel_crtc);
>>
>> @@ -4738,8 +4750,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>> else
>> dspcntr |= DISPPLANE_SEL_PIPE_B;
>>
>> -if (intel_crtc->config.has_dp_encoder)
>> +if (intel_crtc->config.has_dp_encoder) {
>> intel_dp_set_m_n(intel_crtc);
>> +if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
>> +intel_dp_set_m2_n2(intel_crtc,
>> +&intel_crtc->config.dp_m2_n2);
>> +}
>>
>> intel_set_pipe_timings(intel_crtc);
>>
>> @@ -5530,6 +5546,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
>> intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
>> }
>>
>> +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
>> +{
>> +struct drm_device *dev = crtc->base.dev;
>> +struct drm_i915_private *dev_priv = dev->dev_private;
>> +enum transcoder transcoder = crtc->config.cpu_transcoder;
>> +
>> +I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
>> +I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
>> +I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
>> +I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
>> +}
>> +
>> static void vlv_update_pll(struct intel_crtc *crtc)
>> {
>> u32 dpll, dpll_md;
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index b5ec489..1c3960b 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>> }
>> }
>>
>> -static void
>> -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
>> -{
>> -struct drm_device *dev = crtc->base.dev;
>> -struct drm_i915_private *dev_priv = dev->dev_private;
>> -enum transcoder transcoder = crtc->config.cpu_transcoder;
>> -
>> -I915_WRITE(PIPE_DATA_M2(transcoder),
>> -TU_SIZE(m_n->tu) | m_n->gmch_m);
>> -I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
>> -I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
>> -I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
>> -}
>> -
>> bool
>> intel_dp_
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Set M2_N2 registers during mode set
On Mon, 7 Jul 2014 14:59:45 +0530
Vandana Kannan wrote:
> For Gen < 8, set M2_N2 registers on every mode set. This is required to make
> sure M2_N2 registers are set during boot, resume from sleep for cross-
> checking the state. The register is set only if DRRS is supported.
>
> v2: Patch rebased
>
> v3: Daniel's review comments
> - Removed HAS_DRRS(dev) and added bool has_drrs to pipe_config to
> track drrs support
>
> Signed-off-by: Vandana Kannan
> Cc: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_display.c | 36
>
> drivers/gpu/drm/i915/intel_dp.c | 16 ++--
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 36 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a72b55f..22bdea5f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4020,8 +4020,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->config.has_pch_encoder)
> intel_prepare_shared_dpll(intel_crtc);
>
> - if (intel_crtc->config.has_dp_encoder)
> + if (intel_crtc->config.has_dp_encoder) {
> intel_dp_set_m_n(intel_crtc);
> + if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
> + intel_dp_set_m2_n2(intel_crtc,
> + &intel_crtc->config.dp_m2_n2);
> + }
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -4130,8 +4134,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->active)
> return;
>
> - if (intel_crtc->config.has_dp_encoder)
> + if (intel_crtc->config.has_dp_encoder) {
> intel_dp_set_m_n(intel_crtc);
> + if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
> + intel_dp_set_m2_n2(intel_crtc,
> + &intel_crtc->config.dp_m2_n2);
> + }
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -4648,8 +4656,12 @@ static void valleyview_crtc_enable(struct drm_crtc
> *crtc)
> /* Set up the display plane register */
> dspcntr = DISPPLANE_GAMMA_ENABLE;
>
> - if (intel_crtc->config.has_dp_encoder)
> + if (intel_crtc->config.has_dp_encoder) {
> intel_dp_set_m_n(intel_crtc);
> + if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
> + intel_dp_set_m2_n2(intel_crtc,
> + &intel_crtc->config.dp_m2_n2);
> + }
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -4738,8 +4750,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> else
> dspcntr |= DISPPLANE_SEL_PIPE_B;
>
> - if (intel_crtc->config.has_dp_encoder)
> + if (intel_crtc->config.has_dp_encoder) {
> intel_dp_set_m_n(intel_crtc);
> + if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
> + intel_dp_set_m2_n2(intel_crtc,
> + &intel_crtc->config.dp_m2_n2);
> + }
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -5530,6 +5546,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
> intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
> }
>
> +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + enum transcoder transcoder = crtc->config.cpu_transcoder;
> +
> + I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
> + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
> + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
> + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
> +}
> +
> static void vlv_update_pll(struct intel_crtc *crtc)
> {
> u32 dpll, dpll_md;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b5ec489..1c3960b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> }
> }
>
> -static void
> -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
> -{
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - enum transcoder transcoder = crtc->config.cpu_transcoder;
> -
> - I915_WRITE(PIPE_DATA_M2(transcoder),
> - TU_SIZE(m_n->tu) | m_n->gmch_m);
> - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
> - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
> - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
> -}
> -
> bool
> intel_dp_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_config *pipe_config)
> @@ -819
[Intel-gfx] [PATCH 1/2] drm/i915: Set M2_N2 registers during mode set
For Gen < 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is supported.
v2: Patch rebased
v3: Daniel's review comments
- Removed HAS_DRRS(dev) and added bool has_drrs to pipe_config to
track drrs support
Signed-off-by: Vandana Kannan
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 36
drivers/gpu/drm/i915/intel_dp.c | 16 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 36 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a72b55f..22bdea5f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4020,8 +4020,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc->config.has_pch_encoder)
intel_prepare_shared_dpll(intel_crtc);
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config.has_dp_encoder) {
intel_dp_set_m_n(intel_crtc);
+ if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
+ intel_dp_set_m2_n2(intel_crtc,
+ &intel_crtc->config.dp_m2_n2);
+ }
intel_set_pipe_timings(intel_crtc);
@@ -4130,8 +4134,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc->active)
return;
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config.has_dp_encoder) {
intel_dp_set_m_n(intel_crtc);
+ if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
+ intel_dp_set_m2_n2(intel_crtc,
+ &intel_crtc->config.dp_m2_n2);
+ }
intel_set_pipe_timings(intel_crtc);
@@ -4648,8 +4656,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config.has_dp_encoder) {
intel_dp_set_m_n(intel_crtc);
+ if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
+ intel_dp_set_m2_n2(intel_crtc,
+ &intel_crtc->config.dp_m2_n2);
+ }
intel_set_pipe_timings(intel_crtc);
@@ -4738,8 +4750,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
else
dspcntr |= DISPPLANE_SEL_PIPE_B;
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config.has_dp_encoder) {
intel_dp_set_m_n(intel_crtc);
+ if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
+ intel_dp_set_m2_n2(intel_crtc,
+ &intel_crtc->config.dp_m2_n2);
+ }
intel_set_pipe_timings(intel_crtc);
@@ -5530,6 +5546,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
}
+void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+ I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+}
+
static void vlv_update_pll(struct intel_crtc *crtc)
{
u32 dpll, dpll_md;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b5ec489..1c3960b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
-static void
-intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- enum transcoder transcoder = crtc->config.cpu_transcoder;
-
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n->tu) | m_n->gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
-}
-
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
@@ -819,6 +805,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_pch_encoder = true;
pipe_config->has_dp_encoder = true;
+ pipe_config->has
[Intel-gfx] [PATCH 1/2] drm/i915: Set M2_N2 registers during mode set
For Gen < 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is supported.
Signed-off-by: Vandana Kannan
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 30 +++---
drivers/gpu/drm/i915/intel_dp.c | 14 --
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6b0e174..b82f157 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1956,6 +1956,9 @@ struct drm_i915_cmd_table {
#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
#define HAS_RUNTIME_PM(dev)(IS_GEN6(dev) || IS_HASWELL(dev) || \
IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
+#define HAS_DRRS(dev) (to_i915(dev)->drrs.connector && \
+to_i915(dev)->drrs.connector-> \
+panel.downclock_mode)
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 767ca96..cf3ad87 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5278,6 +5278,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
}
+void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+ I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+}
+
static void vlv_update_pll(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
@@ -5872,8 +5884,12 @@ skip_dpll:
dspcntr |= DISPPLANE_SEL_PIPE_B;
}
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config.has_dp_encoder) {
intel_dp_set_m_n(intel_crtc);
+ if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev))
+ intel_dp_set_m2_n2(intel_crtc,
+ &intel_crtc->config.dp_m2_n2);
+ }
intel_set_pipe_timings(intel_crtc);
@@ -6881,8 +6897,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
} else
intel_put_shared_dpll(intel_crtc);
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config.has_dp_encoder) {
intel_dp_set_m_n(intel_crtc);
+ if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev))
+ intel_dp_set_m2_n2(intel_crtc,
+ &intel_crtc->config.dp_m2_n2);
+ }
if (is_lvds && has_reduced_clock && i915.powersave)
intel_crtc->lowfreq_avail = true;
@@ -7377,8 +7397,12 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
return -EINVAL;
intel_ddi_pll_enable(intel_crtc);
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config.has_dp_encoder) {
intel_dp_set_m_n(intel_crtc);
+ if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev))
+ intel_dp_set_m2_n2(intel_crtc,
+ &intel_crtc->config.dp_m2_n2);
+ }
intel_crtc->lowfreq_avail = false;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9f67b72..bcab4ea 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
-static void
-intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- enum transcoder transcoder = crtc->config.cpu_transcoder;
-
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n->tu) | m_n->gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
-}
-
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index acfc5c8..5233a3d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b
