[Intel-gfx] [PATCH 1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

2017-07-06 Thread Rodrigo Vivi 
One warning is that in order to get DPLL Link rates
3240 and 4050 that allows 648000 and 81 is that:
"Some SKUs may require elevated I/O voltage to support
this."

v2: Rebase on top of source_rates changes.

Cc: Clint Taylor 
Cc: Mika Kahola 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dp.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2d42d09..4355bdf 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -97,6 +97,9 @@ struct dp_link_dpll {
  324000, 432000, 54 };
 static const int skl_rates[] = { 162000, 216000, 27,
  324000, 432000, 54 };
+static const int cnl_rates[] = { 162000, 216000, 27,
+324000, 432000, 54,
+648000, 81 };
 static const int default_rates[] = { 162000, 27, 54 };
 
 /**
@@ -238,6 +241,9 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp)
if (IS_GEN9_LP(dev_priv)) {
source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
+   } else if (IS_CANNONLAKE(dev_priv)) {
+   source_rates = cnl_rates;
+   size = ARRAY_SIZE(cnl_rates);
} else if (IS_GEN9_BC(dev_priv)) {
source_rates = skl_rates;
size = ARRAY_SIZE(skl_rates);
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

2017-08-09 Thread Rodrigo Vivi 
Clint or Mika, could you please review this patch and next 2 here?

I remember Clint telling me at some point that rates had possibly
change on spec but I checked here and I still see:
"eDP/DP link bit rates: 1.62, 2.16, 2.7, 3.24, 4.32, 5.4, 6.48*, 8.1* GHz"

Thanks in advance,
Rodrigo.

On Thu, Jul 6, 2017 at 1:54 PM, Rodrigo Vivi  wrote:
> One warning is that in order to get DPLL Link rates
> 3240 and 4050 that allows 648000 and 81 is that:
> "Some SKUs may require elevated I/O voltage to support
> this."
>
> v2: Rebase on top of source_rates changes.
>
> Cc: Clint Taylor 
> Cc: Mika Kahola 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2d42d09..4355bdf 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -97,6 +97,9 @@ struct dp_link_dpll {
>   324000, 432000, 54 };
>  static const int skl_rates[] = { 162000, 216000, 27,
>   324000, 432000, 54 };
> +static const int cnl_rates[] = { 162000, 216000, 27,
> +324000, 432000, 54,
> +648000, 81 };
>  static const int default_rates[] = { 162000, 27, 54 };
>
>  /**
> @@ -238,6 +241,9 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp)
> if (IS_GEN9_LP(dev_priv)) {
> source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> +   } else if (IS_CANNONLAKE(dev_priv)) {
> +   source_rates = cnl_rates;
> +   size = ARRAY_SIZE(cnl_rates);
> } else if (IS_GEN9_BC(dev_priv)) {
> source_rates = skl_rates;
> size = ARRAY_SIZE(skl_rates);
> --
> 1.9.1
>
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

2017-08-10 Thread Mika Kahola 
On Thu, 2017-07-06 at 13:54 -0700, Rodrigo Vivi wrote:
> One warning is that in order to get DPLL Link rates
> 3240 and 4050 that allows 648000 and 81 is that:
> "Some SKUs may require elevated I/O voltage to support
> this."
I also found a mention in BSpec 

"Frequencies over 5.4 GHz only supported on certain DDI ports and SKUs"

The only difference between SKUs that I spotted was related to DDI D
port speeds. If BSpec is correct, then we should somehow separate the
max port speeds for DDI D port.

> 
> v2: Rebase on top of source_rates changes.
> 
> Cc: Clint Taylor 
> Cc: Mika Kahola 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 2d42d09..4355bdf 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -97,6 +97,9 @@ struct dp_link_dpll {
>     324000, 432000, 54 };
>  static const int skl_rates[] = { 162000, 216000, 27,
>     324000, 432000, 54 };
> +static const int cnl_rates[] = { 162000, 216000, 27,
> +  324000, 432000, 54,
> +  648000, 81 };
>  static const int default_rates[] = { 162000, 27, 54 };
>  
>  /**
> @@ -238,6 +241,9 @@ int intel_dp_max_lane_count(struct intel_dp
> *intel_dp)
>   if (IS_GEN9_LP(dev_priv)) {
>   source_rates = bxt_rates;
>   size = ARRAY_SIZE(bxt_rates);
> + } else if (IS_CANNONLAKE(dev_priv)) {
> + source_rates = cnl_rates;
> + size = ARRAY_SIZE(cnl_rates);
>   } else if (IS_GEN9_BC(dev_priv)) {
>   source_rates = skl_rates;
>   size = ARRAY_SIZE(skl_rates);
-- 
Mika Kahola - Intel OTC

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