Re: [Intel-gfx] [PATCH 1/4] drm/i915: Move display pcode requests to intel_de
On Tue, 23 Aug 2022, Maarten Lankhorst
wrote:
> This will allow us not to use uncore from display code directly any more.
Mmh, a bit tedious but I guess this is what we'll need to do. See also
ee421bb4cb95 ("drm/i915/pcode: Extend pcode functions for multiple
gt's").
Reviewed-by: Jani Nikula
BR,
Jain.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/hsw_ips.c| 7 ++-
> drivers/gpu/drm/i915/display/intel_bw.c | 22 -
> drivers/gpu/drm/i915/display/intel_cdclk.c| 45 +--
> drivers/gpu/drm/i915/display/intel_de.h | 30 +
> drivers/gpu/drm/i915/display/intel_display.c | 1 -
> .../drm/i915/display/intel_display_power.c| 3 +-
> .../i915/display/intel_display_power_well.c | 7 ++-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +-
> 8 files changed, 71 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
> b/drivers/gpu/drm/i915/display/hsw_ips.c
> index 861dcd2eb890..ab0032b78d7f 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -8,7 +8,6 @@
> #include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> -#include "intel_pcode.h"
>
> static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
> {
> @@ -28,8 +27,8 @@ static void hsw_ips_enable(const struct intel_crtc_state
> *crtc_state)
>
> if (IS_BROADWELL(i915)) {
> drm_WARN_ON(&i915->drm,
> - snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
> - IPS_ENABLE | IPS_PCODE_CONTROL));
> + intel_de_pcode_write(i915, DISPLAY_IPS_CONTROL,
> + IPS_ENABLE |
> IPS_PCODE_CONTROL));
> /*
>* Quoting Art Runyan: "its not safe to expect any particular
>* value in IPS_CTL bit 31 after enabling IPS through the
> @@ -62,7 +61,7 @@ bool hsw_ips_disable(const struct intel_crtc_state
> *crtc_state)
>
> if (IS_BROADWELL(i915)) {
> drm_WARN_ON(&i915->drm,
> - snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
> 0));
> + intel_de_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));
> /*
>* Wait for PCODE to finish disabling IPS. The BSpec specified
>* 42ms timeout value leads to occasional timeouts so use 100ms
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 79269d2c476b..8ecf4e3e2bc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -10,9 +10,9 @@
> #include "intel_atomic.h"
> #include "intel_bw.h"
> #include "intel_cdclk.h"
> +#include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_mchbar_regs.h"
> -#include "intel_pcode.h"
> #include "intel_pm.h"
>
> /* Parameters for Qclk Geyserville (QGV) */
> @@ -78,9 +78,9 @@ static int icl_pcode_read_qgv_point_info(struct
> drm_i915_private *dev_priv,
> u16 dclk;
> int ret;
>
> - ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> - ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
> - &val, &val2);
> + ret = intel_de_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> + ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
> + &val, &val2);
> if (ret)
> return ret;
>
> @@ -104,8 +104,8 @@ static int adls_pcode_read_psf_gv_point_info(struct
> drm_i915_private *dev_priv,
> int ret;
> int i;
>
> - ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> - ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
> + ret = intel_de_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> + ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val,
> NULL);
> if (ret)
> return ret;
>
> @@ -123,11 +123,11 @@ int icl_pcode_restrict_qgv_points(struct
> drm_i915_private *dev_priv,
> int ret;
>
> /* bspec says to keep retrying for at least 1 ms */
> - ret = skl_pcode_request(&dev_priv->uncore,
> ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> - points_mask,
> - ICL_PCODE_REP_QGV_MASK |
> ADLS_PCODE_REP_PSF_MASK,
> - ICL_PCODE_REP_QGV_SAFE |
> ADLS_PCODE_REP_PSF_SAFE,
> - 1);
> + ret = intel_de_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> + points_mask,
> + ICL_PCODE_REP_QGV_MASK |
> ADLS_PCODE_REP_PSF_MASK,
> + ICL_PCODE_REP_QGV_SAFE |
> ADLS_PCODE_REP_PSF_SAFE,
> +
[Intel-gfx] [PATCH 1/4] drm/i915: Move display pcode requests to intel_de
This will allow us not to use uncore from display code directly any more.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/hsw_ips.c| 7 ++-
drivers/gpu/drm/i915/display/intel_bw.c | 22 -
drivers/gpu/drm/i915/display/intel_cdclk.c| 45 +--
drivers/gpu/drm/i915/display/intel_de.h | 30 +
drivers/gpu/drm/i915/display/intel_display.c | 1 -
.../drm/i915/display/intel_display_power.c| 3 +-
.../i915/display/intel_display_power_well.c | 7 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +-
8 files changed, 71 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
b/drivers/gpu/drm/i915/display/hsw_ips.c
index 861dcd2eb890..ab0032b78d7f 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -8,7 +8,6 @@
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
-#include "intel_pcode.h"
static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
{
@@ -28,8 +27,8 @@ static void hsw_ips_enable(const struct intel_crtc_state
*crtc_state)
if (IS_BROADWELL(i915)) {
drm_WARN_ON(&i915->drm,
- snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
- IPS_ENABLE | IPS_PCODE_CONTROL));
+ intel_de_pcode_write(i915, DISPLAY_IPS_CONTROL,
+IPS_ENABLE |
IPS_PCODE_CONTROL));
/*
* Quoting Art Runyan: "its not safe to expect any particular
* value in IPS_CTL bit 31 after enabling IPS through the
@@ -62,7 +61,7 @@ bool hsw_ips_disable(const struct intel_crtc_state
*crtc_state)
if (IS_BROADWELL(i915)) {
drm_WARN_ON(&i915->drm,
- snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
0));
+ intel_de_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));
/*
* Wait for PCODE to finish disabling IPS. The BSpec specified
* 42ms timeout value leads to occasional timeouts so use 100ms
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 79269d2c476b..8ecf4e3e2bc6 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -10,9 +10,9 @@
#include "intel_atomic.h"
#include "intel_bw.h"
#include "intel_cdclk.h"
+#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_mchbar_regs.h"
-#include "intel_pcode.h"
#include "intel_pm.h"
/* Parameters for Qclk Geyserville (QGV) */
@@ -78,9 +78,9 @@ static int icl_pcode_read_qgv_point_info(struct
drm_i915_private *dev_priv,
u16 dclk;
int ret;
- ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
-ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
-&val, &val2);
+ ret = intel_de_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
+ &val, &val2);
if (ret)
return ret;
@@ -104,8 +104,8 @@ static int adls_pcode_read_psf_gv_point_info(struct
drm_i915_private *dev_priv,
int ret;
int i;
- ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
-ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
+ ret = intel_de_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val,
NULL);
if (ret)
return ret;
@@ -123,11 +123,11 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private
*dev_priv,
int ret;
/* bspec says to keep retrying for at least 1 ms */
- ret = skl_pcode_request(&dev_priv->uncore,
ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
- points_mask,
- ICL_PCODE_REP_QGV_MASK |
ADLS_PCODE_REP_PSF_MASK,
- ICL_PCODE_REP_QGV_SAFE |
ADLS_PCODE_REP_PSF_SAFE,
- 1);
+ ret = intel_de_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+points_mask,
+ICL_PCODE_REP_QGV_MASK |
ADLS_PCODE_REP_PSF_MASK,
+ICL_PCODE_REP_QGV_SAFE |
ADLS_PCODE_REP_PSF_SAFE,
+1);
if (ret < 0) {
drm_err(&dev_priv->drm, "Failed to disable qgv points (%d)
points: 0x%x\n", ret, points_mask);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 86a22c3766e5..15565406679c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drive
