On Fri, 8 Feb 2013 17:35:21 -0200
Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
This is already done on ironlake_irq_handler. We want to make sure the
interrupts are disabled before we check any of the other interrupt
registers.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
b/drivers/gpu/drm/i915/i915_irq.c index 09bd8d4..e9a6ade 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -786,6 +786,7 @@ static irqreturn_t ivybridge_irq_handler(int irq,
void *arg) /* disable master interrupt before clearing iir */
de_ier = I915_READ(DEIER);
I915_WRITE(DEIER, de_ier ~DE_MASTER_IRQ_CONTROL);
+ POSTING_READ(DEIER);
/* On Haswell, also mask ERR_INT because we don't want to
risk
* generating unclaimed register interrupts from inside
the interrupt
The POSTING_READ isn't needed because the very next line will serve as
a posting read, assuming that hasn't changed throughout the series, but
it still looks to be the case as of patch 5.
Also note, the only thing DEIER should effect is the propagation of the
interrupt to the CPU, and not the status bits in registers.
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