Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

2023-06-22 Thread Bhadane, Dnyaneshwar 


> -Original Message-
> From: Tvrtko Ursulin 
> Sent: Friday, June 16, 2023 5:37 PM
> To: Bhadane, Dnyaneshwar ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for
> platform/subplatform defines
> 
> 
> On 16/06/2023 13:05, Tvrtko Ursulin wrote:
> >
> > On 16/06/2023 12:42, Dnyaneshwar Bhadane wrote:
> >> Follow consistent naming convention. Replace MTL with METEORLAKE
> >>
> >> Signed-off-by: Dnyaneshwar Bhadane 
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_fbc.c  |  2 +-
> >>   drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
> >>   drivers/gpu/drm/i915/display/intel_psr.c  | 10 ++---
> >>   .../drm/i915/display/skl_universal_plane.c    |  4 +-
> >>   drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  8 ++--
> >>   drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
> >>   .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
> >>   drivers/gpu/drm/i915/gt/intel_gt_mcr.c    |  4 +-
> >>   drivers/gpu/drm/i915/gt/intel_lrc.c   |  4 +-
> >>   drivers/gpu/drm/i915/gt/intel_rc6.c   |  2 +-
> >>   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44
> >> +--
> >>   drivers/gpu/drm/i915/gt/uc/intel_guc.c    |  4 +-
> >>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
> >>   drivers/gpu/drm/i915/i915_drv.h   |  6 +--
> >>   drivers/gpu/drm/i915/i915_perf.c  |  4 +-
> >>   15 files changed, 51 insertions(+), 51 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> >> b/drivers/gpu/drm/i915/display/intel_fbc.c
> >> index 7f8b2d7713c7..6358a8b26172 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> >> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
> >> intel_atomic_state *state,
> >>   /* Wa_14016291713 */
> >>   if ((IS_DISPLAY_VER(i915, 12, 13) ||
> >> - IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> >> + IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> >>   crtc_state->has_psr) {
> >>   plane_state->no_fbc_reason = "PSR1 enabled
> >> (Wa_14016291713)";
> >>   return 0;
> >> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> index f7608d363634..8c3158b188ef 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private
> >> *i915)
> >>    &pmdemand_state->base,
> >>    &intel_pmdemand_funcs);
> >> -    if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> >> +    if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> >>   /* Wa_14016740474 */
> >>   intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> >> DMD_RSP_TIMEOUT_DISABLE); diff --git
> >> a/drivers/gpu/drm/i915/display/intel_psr.c
> >> b/drivers/gpu/drm/i915/display/intel_psr.c
> >> index cf82cc295319..00c98c2b4324 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> >> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp
> >> *intel_dp,
> >>   bool set_wa_bit = false;
> >>   /* Wa_14015648006 */
> >> -    if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >> +    if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> >>   IS_DISPLAY_VER(dev_priv, 11, 13))
> >>   set_wa_bit |= crtc_state->wm_level_disabled; @@ -1320,7
> >> +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
> >> *intel_dp,
> >>    * All supported adlp panels have 1-based X granularity,
> >> this may
> >>    * cause issues if non-supported panels are used.
> >>    */
> >> -    if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >> +    if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >>   intel_de_rmw(dev_priv,
> >> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
> >>    ADLP_1_BASED_X_GRANULARITY);
> >>   else if (IS_ALDERLAKE_P(dev_priv)) @@ -1328,7 +1328,7 @@
>

Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

2023-06-22 Thread Tvrtko Ursulin 



On 21/06/2023 22:11, Matt Roper wrote:

On Fri, Jun 16, 2023 at 01:05:08PM +0100, Tvrtko Ursulin wrote:


On 16/06/2023 12:42, Dnyaneshwar Bhadane wrote:

Follow consistent naming convention. Replace MTL with
METEORLAKE

Signed-off-by: Dnyaneshwar Bhadane 
---
   drivers/gpu/drm/i915/display/intel_fbc.c  |  2 +-
   drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
   drivers/gpu/drm/i915/display/intel_psr.c  | 10 ++---
   .../drm/i915/display/skl_universal_plane.c|  4 +-
   drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  8 ++--
   drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
   .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
   drivers/gpu/drm/i915/gt/intel_gt_mcr.c|  4 +-
   drivers/gpu/drm/i915/gt/intel_lrc.c   |  4 +-
   drivers/gpu/drm/i915/gt/intel_rc6.c   |  2 +-
   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +--
   drivers/gpu/drm/i915/gt/uc/intel_guc.c|  4 +-
   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
   drivers/gpu/drm/i915/i915_drv.h   |  6 +--
   drivers/gpu/drm/i915/i915_perf.c  |  4 +-
   15 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct 
intel_atomic_state *state,
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(i915, 12, 13) ||
-IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
crtc_state->has_psr) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c 
b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
 &pmdemand_state->base,
 &intel_pmdemand_funcs);
-   if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+   if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
/* Wa_14016740474 */
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, 
DMD_RSP_TIMEOUT_DISABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index cf82cc295319..00c98c2b4324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
bool set_wa_bit = false;
/* Wa_14015648006 */
-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
IS_DISPLAY_VER(dev_priv, 11, 13))
set_wa_bit |= crtc_state->wm_level_disabled;
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp 
*intel_dp,
 * All supported adlp panels have 1-based X granularity, this 
may
 * cause issues if non-supported panels are used.
 */
-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv, 
MTL_CHICKEN_TRANS(cpu_transcoder), 0,
 ADLP_1_BASED_X_GRANULARITY);
else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp 
*intel_dp,
 ADLP_1_BASED_X_GRANULARITY);
/* Wa_16012604467:adlp,mtl[a0,b0] */
-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
 MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp 
*intel_dp)
if (intel_dp->psr.psr2_enabled) {
/* Wa_16012604467:adlp,mtl[a0,b0] */
-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
 MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state 
*state,
goto skip_sel_fetch_set_loop;
/

Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

2023-06-21 Thread Matt Roper 
On Fri, Jun 16, 2023 at 01:05:08PM +0100, Tvrtko Ursulin wrote:
> 
> On 16/06/2023 12:42, Dnyaneshwar Bhadane wrote:
> > Follow consistent naming convention. Replace MTL with
> > METEORLAKE
> > 
> > Signed-off-by: Dnyaneshwar Bhadane 
> > ---
> >   drivers/gpu/drm/i915/display/intel_fbc.c  |  2 +-
> >   drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
> >   drivers/gpu/drm/i915/display/intel_psr.c  | 10 ++---
> >   .../drm/i915/display/skl_universal_plane.c|  4 +-
> >   drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  8 ++--
> >   drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
> >   .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
> >   drivers/gpu/drm/i915/gt/intel_gt_mcr.c|  4 +-
> >   drivers/gpu/drm/i915/gt/intel_lrc.c   |  4 +-
> >   drivers/gpu/drm/i915/gt/intel_rc6.c   |  2 +-
> >   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +--
> >   drivers/gpu/drm/i915/gt/uc/intel_guc.c|  4 +-
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
> >   drivers/gpu/drm/i915/i915_drv.h   |  6 +--
> >   drivers/gpu/drm/i915/i915_perf.c  |  4 +-
> >   15 files changed, 51 insertions(+), 51 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 7f8b2d7713c7..6358a8b26172 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct 
> > intel_atomic_state *state,
> > /* Wa_14016291713 */
> > if ((IS_DISPLAY_VER(i915, 12, 13) ||
> > -IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> > +IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> > crtc_state->has_psr) {
> > plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
> > return 0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c 
> > b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > index f7608d363634..8c3158b188ef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
> >  &pmdemand_state->base,
> >  &intel_pmdemand_funcs);
> > -   if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> > +   if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> > /* Wa_14016740474 */
> > intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, 
> > DMD_RSP_TIMEOUT_DISABLE);
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index cf82cc295319..00c98c2b4324 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp 
> > *intel_dp,
> > bool set_wa_bit = false;
> > /* Wa_14015648006 */
> > -   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > +   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > IS_DISPLAY_VER(dev_priv, 11, 13))
> > set_wa_bit |= crtc_state->wm_level_disabled;
> > @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp 
> > *intel_dp,
> >  * All supported adlp panels have 1-based X granularity, this 
> > may
> >  * cause issues if non-supported panels are used.
> >  */
> > -   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > +   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > intel_de_rmw(dev_priv, 
> > MTL_CHICKEN_TRANS(cpu_transcoder), 0,
> >  ADLP_1_BASED_X_GRANULARITY);
> > else if (IS_ALDERLAKE_P(dev_priv))
> > @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp 
> > *intel_dp,
> >  ADLP_1_BASED_X_GRANULARITY);
> > /* Wa_16012604467:adlp,mtl[a0,b0] */
> > -   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > +   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > intel_de_rmw(dev_priv,
> >  MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
> >  MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> > @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp 
> > *intel_dp)
> > if (intel_dp->psr.psr2_enabled) {
> > /* Wa_16012604467:adlp,mtl[a0,b0] */
> > -   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > +   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > intel_de_rmw(dev_priv,
> >  MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> >  MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS,

Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

2023-06-16 Thread Tvrtko Ursulin 



On 16/06/2023 13:05, Tvrtko Ursulin wrote:


On 16/06/2023 12:42, Dnyaneshwar Bhadane wrote:

Follow consistent naming convention. Replace MTL with
METEORLAKE

Signed-off-by: Dnyaneshwar Bhadane 
---
  drivers/gpu/drm/i915/display/intel_fbc.c  |  2 +-
  drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
  drivers/gpu/drm/i915/display/intel_psr.c  | 10 ++---
  .../drm/i915/display/skl_universal_plane.c    |  4 +-
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  8 ++--
  drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
  .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
  drivers/gpu/drm/i915/gt/intel_gt_mcr.c    |  4 +-
  drivers/gpu/drm/i915/gt/intel_lrc.c   |  4 +-
  drivers/gpu/drm/i915/gt/intel_rc6.c   |  2 +-
  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +--
  drivers/gpu/drm/i915/gt/uc/intel_guc.c    |  4 +-
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
  drivers/gpu/drm/i915/i915_drv.h   |  6 +--
  drivers/gpu/drm/i915/i915_perf.c  |  4 +-
  15 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c

index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct 
intel_atomic_state *state,

  /* Wa_14016291713 */
  if ((IS_DISPLAY_VER(i915, 12, 13) ||
- IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+ IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
  crtc_state->has_psr) {
  plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
  return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c 
b/drivers/gpu/drm/i915/display/intel_pmdemand.c

index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
   &pmdemand_state->base,
   &intel_pmdemand_funcs);
-    if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+    if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
  /* Wa_14016740474 */
  intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, 
DMD_RSP_TIMEOUT_DISABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c

index cf82cc295319..00c98c2b4324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp 
*intel_dp,

  bool set_wa_bit = false;
  /* Wa_14015648006 */
-    if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+    if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
  IS_DISPLAY_VER(dev_priv, 11, 13))
  set_wa_bit |= crtc_state->wm_level_disabled;
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct 
intel_dp *intel_dp,
   * All supported adlp panels have 1-based X granularity, 
this may

   * cause issues if non-supported panels are used.
   */
-    if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+    if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
  intel_de_rmw(dev_priv, 
MTL_CHICKEN_TRANS(cpu_transcoder), 0,

   ADLP_1_BASED_X_GRANULARITY);
  else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct 
intel_dp *intel_dp,

   ADLP_1_BASED_X_GRANULARITY);
  /* Wa_16012604467:adlp,mtl[a0,b0] */
-    if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+    if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
  intel_de_rmw(dev_priv,
   MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
   MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct 
intel_dp *intel_dp)

  if (intel_dp->psr.psr2_enabled) {
  /* Wa_16012604467:adlp,mtl[a0,b0] */
-    if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+    if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
  intel_de_rmw(dev_priv,
   MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
   MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct 
intel_atomic_state *state,

  goto skip_sel_fetch_set_loop;
  /* Wa_14014971492 */
-    if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+    if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
   IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
  crtc_state->splitter.enable)
  pipe_clip.y1 = 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers

Re: [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

2023-06-16 Thread Tvrtko Ursulin 



On 16/06/2023 12:42, Dnyaneshwar Bhadane wrote:

Follow consistent naming convention. Replace MTL with
METEORLAKE

Signed-off-by: Dnyaneshwar Bhadane 
---
  drivers/gpu/drm/i915/display/intel_fbc.c  |  2 +-
  drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
  drivers/gpu/drm/i915/display/intel_psr.c  | 10 ++---
  .../drm/i915/display/skl_universal_plane.c|  4 +-
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  8 ++--
  drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
  .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
  drivers/gpu/drm/i915/gt/intel_gt_mcr.c|  4 +-
  drivers/gpu/drm/i915/gt/intel_lrc.c   |  4 +-
  drivers/gpu/drm/i915/gt/intel_rc6.c   |  2 +-
  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +--
  drivers/gpu/drm/i915/gt/uc/intel_guc.c|  4 +-
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
  drivers/gpu/drm/i915/i915_drv.h   |  6 +--
  drivers/gpu/drm/i915/i915_perf.c  |  4 +-
  15 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct 
intel_atomic_state *state,
  
  	/* Wa_14016291713 */

if ((IS_DISPLAY_VER(i915, 12, 13) ||
-IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
crtc_state->has_psr) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c 
b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
 &pmdemand_state->base,
 &intel_pmdemand_funcs);
  
-	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))

+   if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
/* Wa_14016740474 */
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, 
DMD_RSP_TIMEOUT_DISABLE);
  
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c

index cf82cc295319..00c98c2b4324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
bool set_wa_bit = false;
  
  	/* Wa_14015648006 */

-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
IS_DISPLAY_VER(dev_priv, 11, 13))
set_wa_bit |= crtc_state->wm_level_disabled;
  
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,

 * All supported adlp panels have 1-based X granularity, this 
may
 * cause issues if non-supported panels are used.
 */
-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv, 
MTL_CHICKEN_TRANS(cpu_transcoder), 0,
 ADLP_1_BASED_X_GRANULARITY);
else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp 
*intel_dp,
 ADLP_1_BASED_X_GRANULARITY);
  
  		/* Wa_16012604467:adlp,mtl[a0,b0] */

-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
 MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp 
*intel_dp)
  
  	if (intel_dp->psr.psr2_enabled) {

/* Wa_16012604467:adlp,mtl[a0,b0] */
-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
 MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state 
*state,
goto skip_sel_fetch_set_loop;
  
  	/* Wa_14014971492 */

-   if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+   if ((IS_METEORLAKE_DISPLAY_STEP(dev_pr

[Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines

2023-06-16 Thread Dnyaneshwar Bhadane 
Follow consistent naming convention. Replace MTL with
METEORLAKE

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_fbc.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c  | 10 ++---
 .../drm/i915/display/skl_universal_plane.c|  4 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  8 ++--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c|  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c   |  4 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +--
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
 drivers/gpu/drm/i915/i915_drv.h   |  6 +--
 drivers/gpu/drm/i915/i915_perf.c  |  4 +-
 15 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct 
intel_atomic_state *state,
 
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(i915, 12, 13) ||
-IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
crtc_state->has_psr) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c 
b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
 &pmdemand_state->base,
 &intel_pmdemand_funcs);
 
-   if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+   if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
/* Wa_14016740474 */
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, 
DMD_RSP_TIMEOUT_DISABLE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index cf82cc295319..00c98c2b4324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
bool set_wa_bit = false;
 
/* Wa_14015648006 */
-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
IS_DISPLAY_VER(dev_priv, 11, 13))
set_wa_bit |= crtc_state->wm_level_disabled;
 
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp 
*intel_dp,
 * All supported adlp panels have 1-based X granularity, this 
may
 * cause issues if non-supported panels are used.
 */
-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv, 
MTL_CHICKEN_TRANS(cpu_transcoder), 0,
 ADLP_1_BASED_X_GRANULARITY);
else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp 
*intel_dp,
 ADLP_1_BASED_X_GRANULARITY);
 
/* Wa_16012604467:adlp,mtl[a0,b0] */
-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
 MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp 
*intel_dp)
 
if (intel_dp->psr.psr2_enabled) {
/* Wa_16012604467:adlp,mtl[a0,b0] */
-   if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
 MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state 
*state,
goto skip_sel_fetch_set_loop;
 
/* Wa_14014971492 */
-   if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+   if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 IS_ALD