Re: [Intel-gfx] [PATCH 13/13 v2] drm/i915/skl: Prefer even dividers for SKL DPLLs
On Fri, Jun 26, 2015 at 02:08:30PM -0300, Paulo Zanoni wrote: > 2015-06-25 12:19 GMT-03:00 Damien Lespiau : > > Currently, if an odd divider improves the deviation (minimizes it), we > > take that divider. The recommendation is to prefer even dividers. > > > > v2: Move the check at the right place after having inverted the two for > > loops in the previous patch. > > > > Signed-off-by: Damien Lespiau > > Reviewed-by: Paulo Zanoni Last two patches merged, thanks. -Daniel > > > --- > > drivers/gpu/drm/i915/intel_ddi.c | 7 +++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > b/drivers/gpu/drm/i915/intel_ddi.c > > index 6e964ef..f6b3ccc 100644 > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > @@ -1317,6 +1317,13 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */, > > p); > > } > > } > > + > > + /* > > +* If a solution is found with an even divider, prefer > > +* this one. > > +*/ > > + if (d == 0 && ctx.p) > > + break; > > } > > > > if (!ctx.p) { > > -- > > 2.1.0 > > > > > > -- > Paulo Zanoni > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/13 v2] drm/i915/skl: Prefer even dividers for SKL DPLLs
2015-06-25 12:19 GMT-03:00 Damien Lespiau : > Currently, if an odd divider improves the deviation (minimizes it), we > take that divider. The recommendation is to prefer even dividers. > > v2: Move the check at the right place after having inverted the two for > loops in the previous patch. > > Signed-off-by: Damien Lespiau Reviewed-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_ddi.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index 6e964ef..f6b3ccc 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1317,6 +1317,13 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */, > p); > } > } > + > + /* > +* If a solution is found with an even divider, prefer > +* this one. > +*/ > + if (d == 0 && ctx.p) > + break; > } > > if (!ctx.p) { > -- > 2.1.0 > -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/13 v2] drm/i915/skl: Prefer even dividers for SKL DPLLs
Currently, if an odd divider improves the deviation (minimizes it), we take that divider. The recommendation is to prefer even dividers. v2: Move the check at the right place after having inverted the two for loops in the previous patch. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 6e964ef..f6b3ccc 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1317,6 +1317,13 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */, p); } } + + /* +* If a solution is found with an even divider, prefer +* this one. +*/ + if (d == 0 && ctx.p) + break; } if (!ctx.p) { -- 2.1.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx