subject:"\[Intel\-gfx\] \[PATCH 14\/40\] drm\/i915\: Override display PHY TX FIFO reset master on chv"

Re: [Intel-gfx] [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv

2014-08-01 Thread Ville Syrjälä

On Tue, Jul 29, 2014 at 09:57:09AM -0700, Jesse Barnes wrote:
> On Sat, 28 Jun 2014 02:04:05 +0300
> ville.syrj...@linux.intel.com wrote:
> 
> > From: Ville Syrjälä 
> > 
> > Just an attempt to frob these bits. Apparently we should not need to
> > touch them (apart from maybe making sure the override is disabled so
> > that the hardware automagically does the right thing).
> > 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h   | 12 
> >  drivers/gpu/drm/i915/intel_dp.c   | 23 +++
> >  drivers/gpu/drm/i915/intel_hdmi.c | 23 +++
> >  3 files changed, 58 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 2a7bc22..d246609 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -758,6 +758,8 @@ enum punit_power_well {
> >  #define _VLV_PCS_DW0_CH1   0x8400
> >  #define   DPIO_PCS_TX_LANE2_RESET  (1<<16)
> >  #define   DPIO_PCS_TX_LANE1_RESET  (1<<7)
> > +#define   DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
> > +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2(1<<3)
> >  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
> >  
> >  #define _VLV_PCS01_DW0_CH0 0x200
> > @@ -834,8 +836,18 @@ enum punit_power_well {
> >  
> >  #define _VLV_PCS_DW11_CH0  0x822c
> >  #define _VLV_PCS_DW11_CH1  0x842c
> > +#define   DPIO_LANEDESKEW_STRAP_OVRD   (1<<3)
> > +#define   DPIO_LEFT_TXFIFO_RST_MASTER  (1<<1)
> > +#define   DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
> >  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> >  
> > +#define _VLV_PCS01_DW11_CH00x022c
> > +#define _VLV_PCS23_DW11_CH00x042c
> > +#define _VLV_PCS01_DW11_CH10x262c
> > +#define _VLV_PCS23_DW11_CH10x282c
> > +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, 
> > _VLV_PCS01_DW0_CH1)
> > +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, 
> > _VLV_PCS23_DW0_CH1)
> > +
> >  #define _VLV_PCS_DW12_CH0  0x8230
> >  #define _VLV_PCS_DW12_CH1  0x8430
> >  #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index c59e8fc..814a950 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2139,6 +2139,29 @@ static void chv_pre_enable_dp(struct intel_encoder 
> > *encoder)
> >  
> > mutex_lock(&dev_priv->dpio_lock);
> >  
> > +   /* TX FIFO reset source */
> > +   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > +   val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +   vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> > +
> > +   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> > +   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> > +   val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
> > +   val |= DPIO_LANEDESKEW_STRAP_OVRD;
> > +   vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> > +
> > +   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> > +   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +   val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
> > +   vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> > +
> > +   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> > +   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> > +   val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
> > +   val |= DPIO_LANEDESKEW_STRAP_OVRD;
> > +   vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> > +
> > /* Deassert soft data lane reset*/
> > val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> > val |= CHV_PCS_REQ_SOFTRESET_EN;
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index cda6506..47430d5 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1358,6 +1358,29 @@ static void chv_hdmi_pre_enable(struct intel_encoder 
> > *encoder)
> >  
> > mutex_lock(&dev_priv->dpio_lock);
> >  
> > +   /* TX FIFO reset source */
> > +   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > +   val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +   vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> > +
> > +   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> > +   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> > +   val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
> > +   val |= DPIO_LANEDESKEW_STRAP_OVRD;
> > +   vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> > +
> > +   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> > +   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +   val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
> > +   vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> > +
> > +   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> > +   val &= ~DPIO_LEF

Re: [Intel-gfx] [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv

2014-07-29 Thread Jesse Barnes

On Sat, 28 Jun 2014 02:04:05 +0300
ville.syrj...@linux.intel.com wrote:

> From: Ville Syrjälä 
> 
> Just an attempt to frob these bits. Apparently we should not need to
> touch them (apart from maybe making sure the override is disabled so
> that the hardware automagically does the right thing).
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 12 
>  drivers/gpu/drm/i915/intel_dp.c   | 23 +++
>  drivers/gpu/drm/i915/intel_hdmi.c | 23 +++
>  3 files changed, 58 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2a7bc22..d246609 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -758,6 +758,8 @@ enum punit_power_well {
>  #define _VLV_PCS_DW0_CH1 0x8400
>  #define   DPIO_PCS_TX_LANE2_RESET(1<<16)
>  #define   DPIO_PCS_TX_LANE1_RESET(1<<7)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER2   (1<<4)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2  (1<<3)
>  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
>  
>  #define _VLV_PCS01_DW0_CH0   0x200
> @@ -834,8 +836,18 @@ enum punit_power_well {
>  
>  #define _VLV_PCS_DW11_CH00x822c
>  #define _VLV_PCS_DW11_CH10x842c
> +#define   DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER(1<<1)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER   (1<<0)
>  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
>  
> +#define _VLV_PCS01_DW11_CH0  0x022c
> +#define _VLV_PCS23_DW11_CH0  0x042c
> +#define _VLV_PCS01_DW11_CH1  0x262c
> +#define _VLV_PCS23_DW11_CH1  0x282c
> +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> +
>  #define _VLV_PCS_DW12_CH00x8230
>  #define _VLV_PCS_DW12_CH10x8430
>  #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c59e8fc..814a950 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2139,6 +2139,29 @@ static void chv_pre_enable_dp(struct intel_encoder 
> *encoder)
>  
>   mutex_lock(&dev_priv->dpio_lock);
>  
> + /* TX FIFO reset source */
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> + val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
> + val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> + val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> + val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
> + val |= DPIO_LANEDESKEW_STRAP_OVRD;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> + val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> + val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> + val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> + val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
> + val |= DPIO_LANEDESKEW_STRAP_OVRD;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> +
>   /* Deassert soft data lane reset*/
>   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>   val |= CHV_PCS_REQ_SOFTRESET_EN;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index cda6506..47430d5 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1358,6 +1358,29 @@ static void chv_hdmi_pre_enable(struct intel_encoder 
> *encoder)
>  
>   mutex_lock(&dev_priv->dpio_lock);
>  
> + /* TX FIFO reset source */
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> + val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
> + val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> + val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> + val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
> + val |= DPIO_LANEDESKEW_STRAP_OVRD;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> + val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> + val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> + val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> + val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
> + val |= DPIO_LANEDESKEW_STRAP_OVRD;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> +
>   /* Deassert soft data lane reset*/
>   val

[Intel-gfx] [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv

2014-06-27 Thread ville . syrjala

From: Ville Syrjälä 

Just an attempt to frob these bits. Apparently we should not need to
touch them (apart from maybe making sure the override is disabled so
that the hardware automagically does the right thing).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h   | 12 
 drivers/gpu/drm/i915/intel_dp.c   | 23 +++
 drivers/gpu/drm/i915/intel_hdmi.c | 23 +++
 3 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2a7bc22..d246609 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -758,6 +758,8 @@ enum punit_power_well {
 #define _VLV_PCS_DW0_CH1   0x8400
 #define   DPIO_PCS_TX_LANE2_RESET  (1<<16)
 #define   DPIO_PCS_TX_LANE1_RESET  (1<<7)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER2(1<<3)
 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
 
 #define _VLV_PCS01_DW0_CH0 0x200
@@ -834,8 +836,18 @@ enum punit_power_well {
 
 #define _VLV_PCS_DW11_CH0  0x822c
 #define _VLV_PCS_DW11_CH1  0x842c
+#define   DPIO_LANEDESKEW_STRAP_OVRD   (1<<3)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER  (1<<1)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
 
+#define _VLV_PCS01_DW11_CH00x022c
+#define _VLV_PCS23_DW11_CH00x042c
+#define _VLV_PCS01_DW11_CH10x262c
+#define _VLV_PCS23_DW11_CH10x282c
+#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
+#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
+
 #define _VLV_PCS_DW12_CH0  0x8230
 #define _VLV_PCS_DW12_CH1  0x8430
 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c59e8fc..814a950 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2139,6 +2139,29 @@ static void chv_pre_enable_dp(struct intel_encoder 
*encoder)
 
mutex_lock(&dev_priv->dpio_lock);
 
+   /* TX FIFO reset source */
+   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+   val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
+   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+   vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
+   val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
+   val |= DPIO_LANEDESKEW_STRAP_OVRD;
+   vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
+   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+   val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
+   vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
+
+   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
+   val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
+   val |= DPIO_LANEDESKEW_STRAP_OVRD;
+   vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+
/* Deassert soft data lane reset*/
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
val |= CHV_PCS_REQ_SOFTRESET_EN;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index cda6506..47430d5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1358,6 +1358,29 @@ static void chv_hdmi_pre_enable(struct intel_encoder 
*encoder)
 
mutex_lock(&dev_priv->dpio_lock);
 
+   /* TX FIFO reset source */
+   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+   val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
+   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+   vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
+   val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
+   val |= DPIO_LANEDESKEW_STRAP_OVRD;
+   vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
+   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+   val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
+   vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
+
+   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+   val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
+   val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
+   val |= DPIO_LANEDESKEW_STRAP_OVRD;
+   vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+
/* Deassert soft data lane reset*/
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
val |= CHV_PCS_REQ_SOFTRESET_EN;
-- 
1.8.5.5

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Re: [Intel-gfx] [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv

Re: [Intel-gfx] [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv

[Intel-gfx] [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv

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