On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Minor checkpatch fixes sprinkled on top of the changed lines.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_drv.h | 94
>
> 1 file changed, 46 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index e5a436c33307..33b733d37706 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -300,13 +300,12 @@ struct intel_panel {
>
> /* Connector and platform specific backlight functions
> */
> int (*setup)(struct intel_connector *connector, enum
> pipe pipe);
> - uint32_t (*get)(struct intel_connector *connector);
> - void (*set)(const struct drm_connector_state
> *conn_state, uint32_t level);
> + u32 (*get)(struct intel_connector *connector);
> + void (*set)(const struct drm_connector_state
> *conn_state, u32 level);
> void (*disable)(const struct drm_connector_state
> *conn_state);
> void (*enable)(const struct intel_crtc_state
> *crtc_state,
> const struct drm_connector_state
> *conn_state);
> - uint32_t (*hz_to_pwm)(struct intel_connector
> *connector,
> - uint32_t hz);
> + u32 (*hz_to_pwm)(struct intel_connector *connector, u32
> hz);
> void (*power)(struct intel_connector *, bool enable);
> } backlight;
> };
> @@ -598,7 +597,7 @@ struct intel_initial_plane_config {
>
> struct intel_scaler {
> int in_use;
> - uint32_t mode;
> + u32 mode;
> };
>
> struct intel_crtc_scaler_state {
> @@ -636,7 +635,7 @@ struct intel_crtc_scaler_state {
>
> struct intel_pipe_wm {
> struct intel_wm_level wm[5];
> - uint32_t linetime;
> + u32 linetime;
> bool fbc_wm_enabled;
> bool pipe_enabled;
> bool sprites_enabled;
> @@ -652,7 +651,7 @@ struct skl_plane_wm {
>
> struct skl_pipe_wm {
> struct skl_plane_wm planes[I915_MAX_PLANES];
> - uint32_t linetime;
> + u32 linetime;
> };
>
> enum vlv_wm_level {
> @@ -665,7 +664,7 @@ enum vlv_wm_level {
> struct vlv_wm_state {
> struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
> struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
> - uint8_t num_levels;
> + u8 num_levels;
> bool cxsr;
> };
>
> @@ -878,13 +877,13 @@ struct intel_crtc_state {
> /* Used by SDVO (and if we ever fix it, HDMI). */
> unsigned pixel_multiplier;
>
> - uint8_t lane_count;
> + u8 lane_count;
>
> /*
>* Used by platforms having DP/HDMI PHY with programmable lane
>* latency optimization.
>*/
> - uint8_t lane_lat_optim_mask;
> + u8 lane_lat_optim_mask;
>
> /* minimum acceptable voltage level */
> u8 min_voltage_level;
> @@ -928,7 +927,7 @@ struct intel_crtc_state {
> struct intel_crtc_wm_state wm;
>
> /* Gamma mode programmed on the pipe */
> - uint32_t gamma_mode;
> + u32 gamma_mode;
>
> /* bitmask of visible planes (enum plane_id) */
> u8 active_planes;
> @@ -1014,7 +1013,7 @@ struct intel_plane {
> enum pipe pipe;
> bool has_fbc;
> bool has_ccs;
> - uint32_t frontbuffer_bit;
> + u32 frontbuffer_bit;
>
> struct {
> u32 base, cntl, size;
> @@ -1109,9 +1108,9 @@ enum link_m_n_set {
>
> struct intel_dp_compliance_data {
> unsigned long edid;
> - uint8_t video_pattern;
> - uint16_t hdisplay, vdisplay;
> - uint8_t bpc;
> + u8 video_pattern;
> + u16 hdisplay, vdisplay;
> + u8 bpc;
> };
>
> struct intel_dp_compliance {
> @@ -1124,18 +1123,18 @@ struct intel_dp_compliance {
>
> struct intel_dp {
> i915_reg_t output_reg;
> - uint32_t DP;
> + u32 DP;
> int link_rate;
> - uint8_t lane_count;
> - uint8_t sink_count;
> + u8 lane_count;
> + u8 sink_count;
> bool link_mst;
> bool link_trained;
> bool has_audio;
> bool reset_link_params;
> - uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
> - uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> - uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> - uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> + u8 dpcd[DP_RECEIVER_CAP_SIZE];
> + u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> + u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
> u8 fec_capable;
> /* source rates */
> @@ -1155,7 +1154,7 @@ struct intel_dp {
> /* sink or branch descriptor */
> struct drm_dp_desc desc;
> struct drm_dp_aux aux;
> - uint8_t train_set[4];
> + u8