subject:"\[Intel\-gfx\] \[PATCH 17\/19\] drm\/i915\: Make IS_VALLEYVIEW only take dev

[Intel-gfx] [PATCH 17/19] drm/i915: Make IS_VALLEYVIEW only take dev_priv

2016-10-11 Thread Tvrtko Ursulin

From: Tvrtko Ursulin 

Saves 944 bytes of .rodata strings and 128 bytes of .text.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/i915_gem_fence.c   | 2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c   | 4 ++--
 drivers/gpu/drm/i915/intel_crt.c| 6 +++---
 drivers/gpu/drm/i915/intel_display.c| 6 +++---
 drivers/gpu/drm/i915/intel_dp.c | 8 
 drivers/gpu/drm/i915/intel_hdmi.c   | 2 +-
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
 9 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 96846ecfc224..f9f9a218d5fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2659,7 +2659,7 @@ struct drm_i915_cmd_table {
 #define IS_IVB_GT1(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0156 || \
 INTEL_DEVID(dev_priv) == 0x0152 || \
 INTEL_DEVID(dev_priv) == 0x015a)
-#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
+#define IS_VALLEYVIEW(dev_priv)((dev_priv)->info.is_valleyview)
 #define IS_CHERRYVIEW(dev_priv)((dev_priv)->info.is_cherryview)
 #define IS_HASWELL(dev_priv)   ((dev_priv)->info.is_haswell)
 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c 
b/drivers/gpu/drm/i915/i915_gem_fence.c
index 8df1fa7234e8..d26768567252 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -448,7 +448,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
-   if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
+   if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
/*
 * On BDW+, swizzling is not used. We leave the CPU memory
 * controller in charge of optimizing memory accesses without
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index d41517e11978..6eb11fd326fd 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1349,7 +1349,7 @@ static void i915_capture_reg_state(struct 
drm_i915_private *dev_priv,
 */
 
/* 1: Registers specific to a single generation */
-   if (IS_VALLEYVIEW(dev)) {
+   if (IS_VALLEYVIEW(dev_priv)) {
error->gtier[0] = I915_READ(GTIER);
error->ier = I915_READ(VLV_IER);
error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
@@ -1398,7 +1398,7 @@ static void i915_capture_reg_state(struct 
drm_i915_private *dev_priv,
error->gtier[0] = I915_READ(GTIER);
} else if (IS_GEN2(dev)) {
error->ier = I915_READ16(IER);
-   } else if (!IS_VALLEYVIEW(dev)) {
+   } else if (!IS_VALLEYVIEW(dev_priv)) {
error->ier = I915_READ(IER);
}
error->eir = I915_READ(EIR);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d456786f5813..d92c3edf10ff 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -253,7 +253,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
 
if (HAS_PCH_LPT(dev_priv))
max_clock = 18;
-   else if (IS_VALLEYVIEW(dev))
+   else if (IS_VALLEYVIEW(dev_priv))
/*
 * 270 MHz due to current DPLL limits,
 * DAC limit supposedly 355 MHz.
@@ -423,7 +423,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector 
*connector)
if (HAS_PCH_SPLIT(dev_priv))
return intel_ironlake_crt_detect_hotplug(connector);
 
-   if (IS_VALLEYVIEW(dev))
+   if (IS_VALLEYVIEW(dev_priv))
return valleyview_crt_detect_hotplug(connector);
 
/*
@@ -850,7 +850,7 @@ void intel_crt_init(struct drm_device *dev)
 
if (HAS_PCH_SPLIT(dev_priv))
adpa_reg = PCH_ADPA;
-   else if (IS_VALLEYVIEW(dev))
+   else if (IS_VALLEYVIEW(dev_priv))
adpa_reg = VLV_ADPA;
else
adpa_reg = ADPA;
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index d61a12dbbd72..c3fb9f700c7a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5876,7 +5876,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
dev_priv->max_cdclk_freq = 675000;
} else if (IS_CHERRYVIEW(dev_priv)) {
dev_priv->max_cdclk_freq = 32;
-   } else if (IS_VALLEYVIEW(dev)) {
+   } else if (IS_VALLEYVIEW(dev_priv)) {
dev_priv->max_cdclk_freq = 40;

Re: [Intel-gfx] [PATCH 17/19] drm/i915: Make IS_VALLEYVIEW only take dev_priv

2016-10-12 Thread David Weinehall

On Tue, Oct 11, 2016 at 02:21:50PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 944 bytes of .rodata strings and 128 bytes of .text.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  drivers/gpu/drm/i915/i915_gem_fence.c   | 2 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c   | 4 ++--
>  drivers/gpu/drm/i915/intel_crt.c| 6 +++---
>  drivers/gpu/drm/i915/intel_display.c| 6 +++---
>  drivers/gpu/drm/i915/intel_dp.c | 8 
>  drivers/gpu/drm/i915/intel_hdmi.c   | 2 +-
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
>  9 files changed, 17 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 96846ecfc224..f9f9a218d5fe 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2659,7 +2659,7 @@ struct drm_i915_cmd_table {
>  #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
>INTEL_DEVID(dev_priv) == 0x0152 || \
>INTEL_DEVID(dev_priv) == 0x015a)
> -#define IS_VALLEYVIEW(dev)   (INTEL_INFO(dev)->is_valleyview)
> +#define IS_VALLEYVIEW(dev_priv)  ((dev_priv)->info.is_valleyview)
>  #define IS_CHERRYVIEW(dev_priv)  ((dev_priv)->info.is_cherryview)
>  #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
>  #define IS_BROADWELL(dev_priv)   ((dev_priv)->info.is_broadwell)
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c 
> b/drivers/gpu/drm/i915/i915_gem_fence.c
> index 8df1fa7234e8..d26768567252 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -448,7 +448,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
>   uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>   uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>  
> - if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
> + if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
>   /*
>* On BDW+, swizzling is not used. We leave the CPU memory
>* controller in charge of optimizing memory accesses without
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index d41517e11978..6eb11fd326fd 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1349,7 +1349,7 @@ static void i915_capture_reg_state(struct 
> drm_i915_private *dev_priv,
>*/
>  
>   /* 1: Registers specific to a single generation */
> - if (IS_VALLEYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv)) {
>   error->gtier[0] = I915_READ(GTIER);
>   error->ier = I915_READ(VLV_IER);
>   error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
> @@ -1398,7 +1398,7 @@ static void i915_capture_reg_state(struct 
> drm_i915_private *dev_priv,
>   error->gtier[0] = I915_READ(GTIER);
>   } else if (IS_GEN2(dev)) {
>   error->ier = I915_READ16(IER);
> - } else if (!IS_VALLEYVIEW(dev)) {
> + } else if (!IS_VALLEYVIEW(dev_priv)) {
>   error->ier = I915_READ(IER);
>   }
>   error->eir = I915_READ(EIR);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c 
> b/drivers/gpu/drm/i915/intel_crt.c
> index d456786f5813..d92c3edf10ff 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -253,7 +253,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>  
>   if (HAS_PCH_LPT(dev_priv))
>   max_clock = 18;
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv))
>   /*
>* 270 MHz due to current DPLL limits,
>* DAC limit supposedly 355 MHz.
> @@ -423,7 +423,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector 
> *connector)
>   if (HAS_PCH_SPLIT(dev_priv))
>   return intel_ironlake_crt_detect_hotplug(connector);
>  
> - if (IS_VALLEYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv))
>   return valleyview_crt_detect_hotplug(connector);
>  
>   /*
> @@ -850,7 +850,7 @@ void intel_crt_init(struct drm_device *dev)
>  
>   if (HAS_PCH_SPLIT(dev_priv))
>   adpa_reg = PCH_ADPA;
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv))
>   adpa_reg = VLV_ADPA;
>   else
>   adpa_reg = ADPA;
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index d61a12dbbd72..c3fb9f700c7a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5876,7 +5876,7 @@ static void intel_update_max_cdclk(struct drm_device 
> *dev)
>   dev_priv->max_cdclk_freq = 675000;
>   } els

[Intel-gfx] [PATCH 17/19] drm/i915: Make IS_VALLEYVIEW only take dev_priv

Re: [Intel-gfx] [PATCH 17/19] drm/i915: Make IS_VALLEYVIEW only take dev_priv

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