Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix PLL initialization for HDMI.
On Wed, Oct 04, 2017 at 07:34:27PM +, Ausmus, James wrote:
> On Tue, Oct 3, 2017 at 3:08 PM, Rodrigo Vivi wrote:
> > HDMI Mode selection on CNL is on CFGCR0 for that PLL, not
> > on in a global CTRL1 as it was on SKL.
> >
> > The original patch addressed this difference, but leaving behind
> > this single entry here. So we were checking the wrong bits during
> > the PLL initialization and consequently avoiding the CFGCR1 setup
> > during HDMI initialization. Luckly when only HDMI was in use BIOS
> > had already setup this for us. But the dual display with hot plug
> > were messed up.
> >
> > Fixes: a927c927de34 ("drm/i915/cnl: Initialize PLLs")
> > Cc: Paulo Zanoni
> > Cc: Manasi Navare
> > Cc: Kahola, Mika
> > Signed-off-by: Rodrigo Vivi
>
> Reviewed-by: James Ausmus
both patches merged to dinq. thanks for review.
>
> > ---
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 55997389a29f..032fd915e929 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2000,7 +2000,7 @@ static void cnl_ddi_pll_enable(struct
> > drm_i915_private *dev_priv,
> >
> > /* 3. Configure DPLL_CFGCR0 */
> > /* Avoid touch CFGCR1 if HDMI mode is not enabled */
> > - if (pll->state.hw_state.cfgcr0 & DPLL_CTRL1_HDMI_MODE(pll->id)) {
> > + if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
> > val = pll->state.hw_state.cfgcr1;
> > I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
> > /* 4. Reab back to ensure writes completed */
> > --
> > 2.13.5
> >
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> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
>
>
> James Ausmus
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix PLL initialization for HDMI.
Good catch. Looks good to me as per the Bspec.
Reviewed-by: Manasi Navare
Manasi
On Tue, Oct 03, 2017 at 03:08:59PM -0700, Rodrigo Vivi wrote:
> HDMI Mode selection on CNL is on CFGCR0 for that PLL, not
> on in a global CTRL1 as it was on SKL.
>
> The original patch addressed this difference, but leaving behind
> this single entry here. So we were checking the wrong bits during
> the PLL initialization and consequently avoiding the CFGCR1 setup
> during HDMI initialization. Luckly when only HDMI was in use BIOS
> had already setup this for us. But the dual display with hot plug
> were messed up.
>
> Fixes: a927c927de34 ("drm/i915/cnl: Initialize PLLs")
> Cc: Paulo Zanoni
> Cc: Manasi Navare
> Cc: Kahola, Mika
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 55997389a29f..032fd915e929 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2000,7 +2000,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private
> *dev_priv,
>
> /* 3. Configure DPLL_CFGCR0 */
> /* Avoid touch CFGCR1 if HDMI mode is not enabled */
> - if (pll->state.hw_state.cfgcr0 & DPLL_CTRL1_HDMI_MODE(pll->id)) {
> + if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
> val = pll->state.hw_state.cfgcr1;
> I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
> /* 4. Reab back to ensure writes completed */
> --
> 2.13.5
>
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix PLL initialization for HDMI.
On Tue, Oct 3, 2017 at 3:08 PM, Rodrigo Vivi wrote:
> HDMI Mode selection on CNL is on CFGCR0 for that PLL, not
> on in a global CTRL1 as it was on SKL.
>
> The original patch addressed this difference, but leaving behind
> this single entry here. So we were checking the wrong bits during
> the PLL initialization and consequently avoiding the CFGCR1 setup
> during HDMI initialization. Luckly when only HDMI was in use BIOS
> had already setup this for us. But the dual display with hot plug
> were messed up.
>
> Fixes: a927c927de34 ("drm/i915/cnl: Initialize PLLs")
> Cc: Paulo Zanoni
> Cc: Manasi Navare
> Cc: Kahola, Mika
> Signed-off-by: Rodrigo Vivi
Reviewed-by: James Ausmus
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 55997389a29f..032fd915e929 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2000,7 +2000,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private
> *dev_priv,
>
> /* 3. Configure DPLL_CFGCR0 */
> /* Avoid touch CFGCR1 if HDMI mode is not enabled */
> - if (pll->state.hw_state.cfgcr0 & DPLL_CTRL1_HDMI_MODE(pll->id)) {
> + if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
> val = pll->state.hw_state.cfgcr1;
> I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
> /* 4. Reab back to ensure writes completed */
> --
> 2.13.5
>
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[Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix PLL initialization for HDMI.
HDMI Mode selection on CNL is on CFGCR0 for that PLL, not
on in a global CTRL1 as it was on SKL.
The original patch addressed this difference, but leaving behind
this single entry here. So we were checking the wrong bits during
the PLL initialization and consequently avoiding the CFGCR1 setup
during HDMI initialization. Luckly when only HDMI was in use BIOS
had already setup this for us. But the dual display with hot plug
were messed up.
Fixes: a927c927de34 ("drm/i915/cnl: Initialize PLLs")
Cc: Paulo Zanoni
Cc: Manasi Navare
Cc: Kahola, Mika
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 55997389a29f..032fd915e929 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2000,7 +2000,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private
*dev_priv,
/* 3. Configure DPLL_CFGCR0 */
/* Avoid touch CFGCR1 if HDMI mode is not enabled */
- if (pll->state.hw_state.cfgcr0 & DPLL_CTRL1_HDMI_MODE(pll->id)) {
+ if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
val = pll->state.hw_state.cfgcr1;
I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
/* 4. Reab back to ensure writes completed */
--
2.13.5
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