Re: [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794

2023-03-29 Thread Matt Roper 
On Wed, Mar 29, 2023 at 05:24:51PM -0300, Gustavo Sousa wrote:
> From: Radhakrishna Sripada 
> 
> Wa_22015279794 applies to MTL P from stepping A0 to B0 (exclusive).
> 
> Signed-off-by: Radhakrishna Sripada 
> Signed-off-by: Gustavo Sousa 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 1ec855813632..35a4cfac2d20 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1156,7 +1156,13 @@
>  #define   ENABLE_EU_COUNT_FOR_TDL_FLUSH  REG_BIT(10)
>  #define   DISABLE_ECCREG_BIT(5)
>  #define   FLOAT_BLEND_OPTIMIZATION_ENABLEREG_BIT(4)
> +/*
> + * We have both ENABLE and DISABLE defines below using the same bit because 
> the
> + * meaning depends on the target platform. There are no platform prefix for 
> them
> + * because different steppings of DG2 pick one or the other semantics.
> + */
>  #define   ENABLE_PREFETCH_INTO_ICREG_BIT(3)
> +#define   DISABLE_PREFETCH_INTO_IC   REG_BIT(3)
>  
>  #define EU_PERF_CNTL0PERF_REG(0xe458)
>  #define EU_PERF_CNTL4PERF_REG(0xe45c)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index cafdf66d9562..29d09ddfc8a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2979,6 +2979,11 @@ general_render_compute_wa_init(struct intel_engine_cs 
> *engine, struct i915_wa_li
>   wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>MTL_DISABLE_SAMPLER_SC_OOO);
>  
> + if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + /* Wa_22015279794 */
> + wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> +  DISABLE_PREFETCH_INTO_IC);
> +
>   if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>   IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>   IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> -- 
> 2.40.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794

2023-03-29 Thread Gustavo Sousa 
From: Radhakrishna Sripada 

Wa_22015279794 applies to MTL P from stepping A0 to B0 (exclusive).

Signed-off-by: Radhakrishna Sripada 
Signed-off-by: Gustavo Sousa 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 1ec855813632..35a4cfac2d20 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1156,7 +1156,13 @@
 #define   ENABLE_EU_COUNT_FOR_TDL_FLUSHREG_BIT(10)
 #define   DISABLE_ECC  REG_BIT(5)
 #define   FLOAT_BLEND_OPTIMIZATION_ENABLE  REG_BIT(4)
+/*
+ * We have both ENABLE and DISABLE defines below using the same bit because the
+ * meaning depends on the target platform. There are no platform prefix for 
them
+ * because different steppings of DG2 pick one or the other semantics.
+ */
 #define   ENABLE_PREFETCH_INTO_IC  REG_BIT(3)
+#define   DISABLE_PREFETCH_INTO_IC REG_BIT(3)
 
 #define EU_PERF_CNTL0  PERF_REG(0xe458)
 #define EU_PERF_CNTL4  PERF_REG(0xe45c)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cafdf66d9562..29d09ddfc8a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2979,6 +2979,11 @@ general_render_compute_wa_init(struct intel_engine_cs 
*engine, struct i915_wa_li
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 MTL_DISABLE_SAMPLER_SC_OOO);
 
+   if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+   /* Wa_22015279794 */
+   wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
+DISABLE_PREFETCH_INTO_IC);
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
-- 
2.40.0

Re: [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794

2023-01-20 Thread Rodrigo Vivi 
On Thu, Jan 19, 2023 at 05:06:39PM -0800, Radhakrishna Sripada wrote:
> This patch adds the workaround to disable IC prefetch.
> 
> Original Author: Madhumitha Tolakanhalli Pradeep

ditto

> Signed-off-by: Radhakrishna Sripada 
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index c52c5f9ad9ce..47ff4ca2bd61 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1677,6 +1677,10 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct 
> i915_wa_list *wal)
>   IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))
>   wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>  
> + /* Wa_22015279794: mtl-p[a0] */
> + if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))
> + wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> +  ENABLE_PREFETCH_INTO_IC);
>   /*
>* Unlike older platforms, we no longer setup implicit steering here;
>* all MCR accesses are explicitly steered.
> -- 
> 2.34.1
>

[Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794

2023-01-19 Thread Radhakrishna Sripada 
This patch adds the workaround to disable IC prefetch.

Original Author: Madhumitha Tolakanhalli Pradeep
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c52c5f9ad9ce..47ff4ca2bd61 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1677,6 +1677,10 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))
wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
+   /* Wa_22015279794: mtl-p[a0] */
+   if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))
+   wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
+ENABLE_PREFETCH_INTO_IC);
/*
 * Unlike older platforms, we no longer setup implicit steering here;
 * all MCR accesses are explicitly steered.
-- 
2.34.1