Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Skip Wa_1604555607 verification at A0
On 2019-10-02 at 09:54:12 +0100, Tvrtko Ursulin wrote:
>
> On 01/10/2019 18:36, Chris Wilson wrote:
> > Quoting Ramalingam C (2019-10-01 18:26:24)
> > > Read of FF_MODE2 register is broken at TGL A0. Hence verification of the
> > > Wa_1604555607 associated to that register needs to be skipped.
> > >
> > > Signed-off-by: Ramalingam C
> > > cc: Tvrtko Ursulin
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 -
> > > drivers/gpu/drm/i915/i915_drv.h | 6 ++
> > > 2 files changed, 27 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 4049b876492a..c63d8c3df4d3 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -991,10 +991,21 @@ wa_list_apply(struct intel_uncore *uncore, const
> > > struct i915_wa_list *wal)
> > > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> > > intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
> > > - if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> > > + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
> > > +
> > > + /*
> > > +* Read of FF_MODE2 is broken on TGL A0.
> > > +* Hence skip the corresponding WA verification.
> > > +*/
> > > + if (IS_TGL_REVID(uncore->i915, 0, TGL_REVID_A0) &&
> > > + i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
> > > + wa->mask == FF_MODE2_TDS_TIMER_MASK)
> > > + continue;
> >
> > This does not scale very well. You will note that wa_verify() already
> > includes a detail on which bits can be read back from HW.
>
> For the record Chris is referring to wa->read which you can set to zero for
> this particular wa and this should automagically work.
Thanks Tvrtko. We could set that wa->read = 0, only for required steppings.
-Ram
>
> Then in IGT/gem_workarounds.c you also have existing framework for marking
> registers as write-only. It may need extending to account for steppings and
> so.
>
> Regards,
>
> Tvrtko
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Skip Wa_1604555607 verification at A0
On 01/10/2019 18:36, Chris Wilson wrote:
Quoting Ramalingam C (2019-10-01 18:26:24)
Read of FF_MODE2 register is broken at TGL A0. Hence verification of the
Wa_1604555607 associated to that register needs to be skipped.
Signed-off-by: Ramalingam C
cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 -
drivers/gpu/drm/i915/i915_drv.h | 6 ++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4049b876492a..c63d8c3df4d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -991,10 +991,21 @@ wa_list_apply(struct intel_uncore *uncore, const struct
i915_wa_list *wal)
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
- if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
+
+ /*
+* Read of FF_MODE2 is broken on TGL A0.
+* Hence skip the corresponding WA verification.
+*/
+ if (IS_TGL_REVID(uncore->i915, 0, TGL_REVID_A0) &&
+ i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
+ wa->mask == FF_MODE2_TDS_TIMER_MASK)
+ continue;
This does not scale very well. You will note that wa_verify() already
includes a detail on which bits can be read back from HW.
For the record Chris is referring to wa->read which you can set to zero
for this particular wa and this should automagically work.
Then in IGT/gem_workarounds.c you also have existing framework for
marking registers as write-only. It may need extending to account for
steppings and so.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Skip Wa_1604555607 verification at A0
Quoting Ramalingam C (2019-10-01 18:26:24)
> Read of FF_MODE2 register is broken at TGL A0. Hence verification of the
> Wa_1604555607 associated to that register needs to be skipped.
>
> Signed-off-by: Ramalingam C
> cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 -
> drivers/gpu/drm/i915/i915_drv.h | 6 ++
> 2 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4049b876492a..c63d8c3df4d3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -991,10 +991,21 @@ wa_list_apply(struct intel_uncore *uncore, const struct
> i915_wa_list *wal)
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
> - if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
> +
> + /*
> +* Read of FF_MODE2 is broken on TGL A0.
> +* Hence skip the corresponding WA verification.
> +*/
> + if (IS_TGL_REVID(uncore->i915, 0, TGL_REVID_A0) &&
> + i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
> + wa->mask == FF_MODE2_TDS_TIMER_MASK)
> + continue;
This does not scale very well. You will note that wa_verify() already
includes a detail on which bits can be read back from HW.
-Chris
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[Intel-gfx] [PATCH 2/2] drm/i915/tgl: Skip Wa_1604555607 verification at A0
Read of FF_MODE2 register is broken at TGL A0. Hence verification of the
Wa_1604555607 associated to that register needs to be skipped.
Signed-off-by: Ramalingam C
cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 -
drivers/gpu/drm/i915/i915_drv.h | 6 ++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4049b876492a..c63d8c3df4d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -991,10 +991,21 @@ wa_list_apply(struct intel_uncore *uncore, const struct
i915_wa_list *wal)
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
- if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
+
+ /*
+* Read of FF_MODE2 is broken on TGL A0.
+* Hence skip the corresponding WA verification.
+*/
+ if (IS_TGL_REVID(uncore->i915, 0, TGL_REVID_A0) &&
+ i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
+ wa->mask == FF_MODE2_TDS_TIMER_MASK)
+ continue;
+
wa_verify(wa,
intel_uncore_read_fw(uncore, wa->reg),
wal->name, "application");
+ }
}
intel_uncore_forcewake_put__locked(uncore, fw);
@@ -1553,6 +1564,15 @@ static int engine_wa_list_verify(struct intel_context
*ce,
if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
continue;
+ /*
+* Read of FF_MODE2 is broken on TGL A0.
+* Hence skip the corresponding WA verification.
+*/
+ if (IS_TGL_REVID(rq->i915, 0, TGL_REVID_A0) &&
+ i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
+ wa->mask == FF_MODE2_TDS_TIMER_MASK)
+ continue;
+
if (!wa_verify(wa, results[i], wal->name, from))
err = -ENXIO;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 337d8306416a..05bf0b398ce7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2065,6 +2065,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ICL_REVID(p, since, until) \
(IS_ICELAKE(p) && IS_REVID(p, since, until))
+#define TGL_REVID_A0 0x0
+#define TGL_REVID_B0 0x1
+
+#define IS_TGL_REVID(p, since, until) \
+ (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
+
#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
--
2.20.1
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