Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb document.
On Thu, Nov 07, 2013 at 10:25:44AM +0800, Lee, Chon Ming wrote: > On 11/06 14:02, Ville Syrjälä wrote: > > > > -#define _DPIO_IREF_CTL_A 0x8040 > > > -#define _DPIO_IREF_CTL_B 0x8060 > > > -#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, > > > _DPIO_IREF_CTL_B) > > > +#define _VLV_PLL_DW10_CH00x8040 > > > +#define _VLV_PLL_DW10_CH10x8060 > > > +#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) > > > > Configdb starts counting from DW8 at 0x8040/60, which kind of make sense > > since the first PLL block ends at DW7. > > > The spreadsheet I refer to is using DW10. The spreadsheet might be incorrect. > Looking at the register offset, it won't be anymore space left after first PLL > block. Make sense for DW8 for second PLL block. The spreadsheet is a bit weird. I was just looking at the web configdb. That at least has some sense in the offsets (apart from the ref block). The spreadsheet also uses hex numbers to count the dwords, which doesn't match what you've done for the > 8 numbers. So I'd go with the web configdb numbers since they're a bit more consistent. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb document.
On 11/06 14:02, Ville Syrjälä wrote: > > -#define _DPIO_IREF_CTL_A 0x8040 > > -#define _DPIO_IREF_CTL_B 0x8060 > > -#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B) > > +#define _VLV_PLL_DW10_CH0 0x8040 > > +#define _VLV_PLL_DW10_CH1 0x8060 > > +#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) > > Configdb starts counting from DW8 at 0x8040/60, which kind of make sense > since the first PLL block ends at DW7. > The spreadsheet I refer to is using DW10. The spreadsheet might be incorrect. Looking at the register offset, it won't be anymore space left after first PLL block. Make sense for DW8 for second PLL block. > > > > -#define DPIO_IREF_BCAST0xc044 > > -#define _DPIO_IREF_A 0x8044 > > -#define _DPIO_IREF_B 0x8064 > > -#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B) > > +#define VLV_PLL_DW11_BCAST 0xc044 > > +#define _VLV_PLL_DW11_CH0 0x8044 > > +#define _VLV_PLL_DW11_CH1 0x8064 > > +#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) > > ... which would make this DW9 > > > > > -#define _DPIO_PLL_CML_A0x804c > > -#define _DPIO_PLL_CML_B0x806c > > -#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B) > > +#define _VLV_PLL_DW13_CH0 0x804c > > +#define _VLV_PLL_DW13_CH1 0x806c > > +#define VLV_PLL_DW13(ch) _PIPE(ch, _VLV_PLL_DW13_CH0, _VLV_PLL_DW13_CH1) > jj > ... DW11 > > > > > -#define _DPIO_LPF_COEFF_A 0x8048 > > -#define _DPIO_LPF_COEFF_B 0x8068 > > -#define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, > > _DPIO_LPF_COEFF_B) > > +#define _VLV_PLL_DW12_CH0 0x8048 > > +#define _VLV_PLL_DW12_CH1 0x8068 > > +#define VLV_PLL_DW12(ch) _PIPE(ch, _VLV_PLL_DW12_CH0, _VLV_PLL_DW12_CH1) > > ... DW10 > > Maybe also reorder this with the previous one to keep the PLL > register defiens in numerical order. > > > > > -#define DPIO_CALIBRATION 0x80ac > > +#define VLV_REF_DW11 0x80ac > > And this is DW13 in configdb. So in the ref block it starts counting from > DW10 for some reason. Yay for consistency. Going to add a comment for the DW to start counting. The spreadsheet I am using start counting at DW8. :( > > The rest looks good to me. I double checked the cpp output to make sure > that the actual changes were limited to i915_debugfs.c. > > > > > -#define DPIO_FASTCLK_DISABLE 0x8100 > > +#define VLV_CMN_DW00x8100 > > > > /* > > * Per DDI channel DPIO regs > > */ > > > > -#define _DPIO_PCS_TX_0 0x8200 > > -#define _DPIO_PCS_TX_1 0x8400 > > +#define _VLV_PCS_DW0_CH0 0x8200 > > +#define _VLV_PCS_DW0_CH1 0x8400 > > #define DPIO_PCS_TX_LANE2_RESET (1<<16) > > #define DPIO_PCS_TX_LANE1_RESET (1<<7) > > -#define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1) > > +#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) > > > > -#define _DPIO_PCS_CLK_00x8204 > > -#define _DPIO_PCS_CLK_10x8404 > > +#define _VLV_PCS_DW1_CH0 0x8204 > > +#define _VLV_PCS_DW1_CH1 0x8404 > > #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN(1<<22) > > #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) > > #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) > > #define DPIO_PCS_CLK_SOFT_RESET (1<<5) > > -#define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1) > > - > > -#define _DPIO_PCS_CTL_OVR1_A 0x8224 > > -#define _DPIO_PCS_CTL_OVR1_B 0x8424 > > -#define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \ > > - _DPIO_PCS_CTL_OVR1_B) > > - > > -#define _DPIO_PCS_STAGGER0_A 0x822c > > -#define _DPIO_PCS_STAGGER0_B 0x842c > > -#define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \ > > - _DPIO_PCS_STAGGER0_B) > > - > > -#define _DPIO_PCS_STAGGER1_A 0x8230 > > -#define _DPIO_PCS_STAGGER1_B 0x8430 > > -#define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \ > > - _DPIO_PCS_STAGGER1_B) > > - > > -#define _DPIO_PCS_CLOCKBUF0_A 0x8238 > > -#define _DPIO_PCS_CLOCKBUF0_B 0x8438 > > -#define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \ > > - _DPIO_PCS_CLOCKBUF0_B) > > - > > -#define _DPIO_PCS_CLOCKBUF8_A 0x825c > > -#define _DPIO_PCS_CLOCKBUF8_B 0x845c > > -#define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \ > > - _DPIO_PCS_CLOCKBUF8_B) > > - > > -#define _DPIO_TX_SWING_CTL2_
Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb document.
On Wed, Nov 06, 2013 at 02:37:36PM +0800, Chon Ming Lee wrote: > Some VLV PHY/PLL DPIO registers have group/lane/channel access. Current > DPIO register definition doesn't have a structure way to break them > down. As a result it is not easy to match the PHY/PLL registers with the > configdb document. Rename those registers based on the configdb for easy > cross references, and without the need to check the offset in the header > file. > > New format is as following. > > __DW doc>_ > > For example, > > VLV_PCS_DW0 - Group access to PCS for lane 0 to 3 for PCS DWORD 0. > VLV_PCS01_DW0_CH0 - PCS access to lane 0/1, channel 0 for PCS DWORD 0. > > Another example is > > VLV_TX_DW0 - Group access to TX lane 0 to 3 for TX DWORD 0 > VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0. > > There is no functional change on this patch. > > v2: Rebase based on previous patch change. > > Suggested-by: Ville Syrjälä > Signed-off-by: Chon Ming Lee > --- > drivers/gpu/drm/i915/i915_debugfs.c | 40 > drivers/gpu/drm/i915/i915_reg.h | 190 > -- > drivers/gpu/drm/i915/intel_display.c | 48 +- > drivers/gpu/drm/i915/intel_dp.c | 32 +++--- > drivers/gpu/drm/i915/intel_hdmi.c| 54 -- > 5 files changed, 171 insertions(+), 193 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b/drivers/gpu/drm/i915/i915_debugfs.c > index 7008aac..d756e23 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1650,28 +1650,28 @@ static int i915_dpio_info(struct seq_file *m, void > *data) > > seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); > > - seq_printf(m, "DPIO_DIV_A: 0x%08x\n", > -vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); > - seq_printf(m, "DPIO_DIV_B: 0x%08x\n", > -vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); > - > - seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", > -vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); > - seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", > -vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); > - > - seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", > -vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); > - seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", > -vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); > - > - seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", > -vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); > - seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", > -vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); > + seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n", > +vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0))); > + seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n", > +vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1))); > + > + seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n", > +vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0))); > + seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n", > +vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1))); > + > + seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n", > +vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0))); > + seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n", > +vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1))); > + > + seq_printf(m, "DPIO PLL DW12 CH0: 0x%08x\n", > +vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW12(0))); > + seq_printf(m, "DPIO PLL DW12 CH1: 0x%08x\n", > +vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW12(1))); > > seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", > -vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); > +vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0)); > > mutex_unlock(&dev_priv->dpio_lock); > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 969ca2e..c71b729 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -452,18 +452,13 @@ > #define DPIO_SFR_BYPASS (1<<1) > #define DPIO_CMNRST (1<<0) > > -#define _DPIO_TX3_SWING_CTL4_A 0x690 > -#define _DPIO_TX3_SWING_CTL4_B 0x2a90 > -#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \ > - _DPIO_TX3_SWING_CTL4_B) > - > #define DPIO_PHY(pipe) ((pipe) >> 1) > #define DPIO_PHY_IOSF_PORT(phy) > (dev_priv->dpio_phy_iosf_port[phy]) > > /* > * Per pipe/PLL DPIO regs > */ > -#define _DPIO_DIV_A 0x800c > +#define _VLV_PLL_DW3_CH0 0x800c > #define DPIO_POST_DIV_SHIFT(28) /* 3 bits */ > #define DPIO_POST_DIV_DAC 0 > #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ > @@ -476,10 +471,10 @@ > #define DPIO
[Intel-gfx] [PATCH 2/2] drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb document.
Some VLV PHY/PLL DPIO registers have group/lane/channel access. Current DPIO register definition doesn't have a structure way to break them down. As a result it is not easy to match the PHY/PLL registers with the configdb document. Rename those registers based on the configdb for easy cross references, and without the need to check the offset in the header file. New format is as following. __DW_ For example, VLV_PCS_DW0 - Group access to PCS for lane 0 to 3 for PCS DWORD 0. VLV_PCS01_DW0_CH0 - PCS access to lane 0/1, channel 0 for PCS DWORD 0. Another example is VLV_TX_DW0 - Group access to TX lane 0 to 3 for TX DWORD 0 VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0. There is no functional change on this patch. v2: Rebase based on previous patch change. Suggested-by: Ville Syrjälä Signed-off-by: Chon Ming Lee --- drivers/gpu/drm/i915/i915_debugfs.c | 40 drivers/gpu/drm/i915/i915_reg.h | 190 -- drivers/gpu/drm/i915/intel_display.c | 48 +- drivers/gpu/drm/i915/intel_dp.c | 32 +++--- drivers/gpu/drm/i915/intel_hdmi.c| 54 -- 5 files changed, 171 insertions(+), 193 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 7008aac..d756e23 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1650,28 +1650,28 @@ static int i915_dpio_info(struct seq_file *m, void *data) seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); - seq_printf(m, "DPIO_DIV_A: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); - seq_printf(m, "DPIO_DIV_B: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); - - seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); - seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); - - seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); - seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); - - seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); - seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); + seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0))); + seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1))); + + seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0))); + seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1))); + + seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0))); + seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1))); + + seq_printf(m, "DPIO PLL DW12 CH0: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW12(0))); + seq_printf(m, "DPIO PLL DW12 CH1: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW12(1))); seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); + vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0)); mutex_unlock(&dev_priv->dpio_lock); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 969ca2e..c71b729 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -452,18 +452,13 @@ #define DPIO_SFR_BYPASS (1<<1) #define DPIO_CMNRST (1<<0) -#define _DPIO_TX3_SWING_CTL4_A 0x690 -#define _DPIO_TX3_SWING_CTL4_B 0x2a90 -#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \ - _DPIO_TX3_SWING_CTL4_B) - #define DPIO_PHY(pipe) ((pipe) >> 1) #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) /* * Per pipe/PLL DPIO regs */ -#define _DPIO_DIV_A0x800c +#define _VLV_PLL_DW3_CH0 0x800c #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ #define DPIO_POST_DIV_DAC0 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ @@ -476,10 +471,10 @@ #define DPIO_ENABLE_CALIBRATION (1<<11) #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ #define DPIO_M2DIV_MASK 0xff -#define _DPIO_DIV_B0x802c -#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) +#d
[Intel-gfx] [PATCH 2/2] drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb document.
Some VLV PHY/PLL DPIO registers have group/lane/channel access. Current DPIO register definition doesn't have a structure way to break them down. As a result it is not easy to match the PHY/PLL registers with the configdb document. Rename those registers based on the configdb for easy cross references, and without the need to check the offset in the header file. New format is as following. __DW_ For example, VLV_PCS_DW0 - Group access to PCS for lane 0 to 3 for PCS DWORD 0. VLV_PCS01_DW0_CH0 - PCS access to lane 0/1, channel 0 for PCS DWORD 0. Another example is VLV_TX_DW0 - Group access to TX lane 0 to 3 for TX DWORD 0 VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0. There is no functional change on this patch. Suggested-by: Ville Syrjälä Signed-off-by: Chon Ming Lee --- drivers/gpu/drm/i915/i915_debugfs.c | 40 drivers/gpu/drm/i915/i915_reg.h | 189 -- drivers/gpu/drm/i915/intel_display.c | 48 +- drivers/gpu/drm/i915/intel_dp.c | 32 +++--- drivers/gpu/drm/i915/intel_hdmi.c| 54 -- 5 files changed, 171 insertions(+), 192 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5c45e9e..f6c4486 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1650,28 +1650,28 @@ static int i915_dpio_info(struct seq_file *m, void *data) seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); - seq_printf(m, "DPIO_DIV_A: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); - seq_printf(m, "DPIO_DIV_B: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); - - seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); - seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); - - seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); - seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); - - seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); - seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); + seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0))); + seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1))); + + seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0))); + seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1))); + + seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0))); + seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1))); + + seq_printf(m, "DPIO PLL DW12 CH0: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW12(0))); + seq_printf(m, "DPIO PLL DW12 CH1: 0x%08x\n", + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW12(1))); seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", - vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); + vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0)); mutex_unlock(&dev_priv->dpio_lock); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dd8ff3b..98d0c78 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -442,17 +442,13 @@ #define DPIO_SFR_BYPASS (1<<1) #define DPIO_CMNRST (1<<0) -#define _DPIO_TX3_SWING_CTL4_A 0x690 -#define _DPIO_TX3_SWING_CTL4_B 0x2a90 -#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \ - _DPIO_TX3_SWING_CTL4_B) #define DPIO_PHY_PORT(pipe)(dev_priv->vlv_phy[pipe >> 1]) /* * Per pipe/PLL DPIO regs */ -#define _DPIO_DIV_A0x800c +#define _VLV_PLL_DW3_CH0 0x800c #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ #define DPIO_POST_DIV_DAC0 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ @@ -465,10 +461,10 @@ #define DPIO_ENABLE_CALIBRATION (1<<11) #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ #define DPIO_M2DIV_MASK 0xff -#define _DPIO_DIV_B0x802c -#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) +#define _VLV_PLL_DW3_CH1 0x802c +#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH
