Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
On Thu, Aug 25, 2022 at 07:04:33PM +0300, Govindapillai, Vinod wrote:
> On Thu, 2022-08-25 at 18:17 +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Aug 25, 2022 at 05:58:19PM +0300, Govindapillai, Vinod wrote:
> > > Hi Stan,
> > >
> > > Some comments inline..
> > >
> > > On Mon, 2022-08-22 at 12:40 +0300, Stanislav Lisovskiy wrote:
> > > > Whenever we are not able to get enough timeslots
> > > > for required PBN, let's try to allocate those
> > > > using DSC, just same way as we do for SST.
> > > >
> > > > v2: Removed intel_dp_mst_dsc_compute_config and refactored
> > > > intel_dp_dsc_compute_config to support timeslots as a
> > > > parameter(Ville Syrjälä)
> > > >
> > > > v3: - Rebased
> > > > - Added a debug to see that we at least try reserving
> > > > VCPI slots using DSC, because currently its not visible
> > > > from the logs, thus making debugging more tricky.
> > > > - Moved timeslots to numerator, where it should be.
> > > >
> > > > v4: - Call drm_dp_mst_atomic_check already during link
> > > > config computation, because we need to know already
> > > > by this moment if uncompressed amount of VCPI slots
> > > > needed can fit, otherwise we need to use DSC.
> > > > (thanks to Vinod Govindapillai for pointing this out)
> > > >
> > > > v5: - Put pipe_config->bigjoiner_pipes back to original
> > > > condition in intel_dp_dsc_compute_config
> > > > (don't remember when I lost it)
> > > >
> > > > Signed-off-by: Stanislav Lisovskiy
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 73 -
> > > > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
> > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
> > > > 3 files changed, 205 insertions(+), 42 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 32292c0be2bd..519b436fc530 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> > > > }
> > > >
> > > > static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> > > > -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
> > > > dsc_max_bpc);
> > > >
> > > > /* Is link rate UHBR and thus 128b/132b? */
> > > > bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> > > > @@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct
> > > > drm_i915_private *i915)
> > > > return 6144 * 8;
> > > > }
> > > >
> > > > -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > > > - u32 link_clock, u32 lane_count,
> > > > - u32 mode_clock, u32
> > > > mode_hdisplay,
> > > > - bool bigjoiner,
> > > > - u32 pipe_bpp)
> > > > +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > > > + u32 link_clock, u32 lane_count,
> > > > + u32 mode_clock, u32 mode_hdisplay,
> > > > + bool bigjoiner,
> > > > + u32 pipe_bpp,
> > > > + u32 timeslots)
> > > > {
> > > > u32 bits_per_pixel, max_bpp_small_joiner_ram;
> > > > int i;
> > > > @@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> > > > drm_i915_private *i915,
> > > > * for SST -> TimeSlotsPerMTP is 1,
> > > > * for MST -> TimeSlotsPerMTP has to be calculated
> > > > */
> > > > - bits_per_pixel = (link_clock * lane_count * 8) /
> > > > + bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
> > > > intel_dp_mode_to_fec_clock(mode_clock);
> > > > + drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
> > > >
> > > > /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz.
> > > > width */
> > > > max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
> > > > @@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> > > > drm_i915_private *i915,
> > > > return bits_per_pixel << 4;
> > > > }
> > > >
> > > > -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > > > - int mode_clock, int
> > > > mode_hdisplay,
> > > > - bool bigjoiner)
> > > > +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > > > + int mode_clock, int mode_hdisplay,
> > > > + bool bigjoiner)
> > > > {
> > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > > u8 min_slice_count, i;
> > > > @@ -961,8 +962,8 @@
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
On Thu, 2022-08-25 at 18:17 +0300, Lisovskiy, Stanislav wrote:
> On Thu, Aug 25, 2022 at 05:58:19PM +0300, Govindapillai, Vinod wrote:
> > Hi Stan,
> >
> > Some comments inline..
> >
> > On Mon, 2022-08-22 at 12:40 +0300, Stanislav Lisovskiy wrote:
> > > Whenever we are not able to get enough timeslots
> > > for required PBN, let's try to allocate those
> > > using DSC, just same way as we do for SST.
> > >
> > > v2: Removed intel_dp_mst_dsc_compute_config and refactored
> > > intel_dp_dsc_compute_config to support timeslots as a
> > > parameter(Ville Syrjälä)
> > >
> > > v3: - Rebased
> > > - Added a debug to see that we at least try reserving
> > > VCPI slots using DSC, because currently its not visible
> > > from the logs, thus making debugging more tricky.
> > > - Moved timeslots to numerator, where it should be.
> > >
> > > v4: - Call drm_dp_mst_atomic_check already during link
> > > config computation, because we need to know already
> > > by this moment if uncompressed amount of VCPI slots
> > > needed can fit, otherwise we need to use DSC.
> > > (thanks to Vinod Govindapillai for pointing this out)
> > >
> > > v5: - Put pipe_config->bigjoiner_pipes back to original
> > > condition in intel_dp_dsc_compute_config
> > > (don't remember when I lost it)
> > >
> > > Signed-off-by: Stanislav Lisovskiy
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 73 -
> > > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
> > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
> > > 3 files changed, 205 insertions(+), 42 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 32292c0be2bd..519b436fc530 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> > > }
> > >
> > > static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> > > -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
> > > dsc_max_bpc);
> > >
> > > /* Is link rate UHBR and thus 128b/132b? */
> > > bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> > > @@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private
> > > *i915)
> > > return 6144 * 8;
> > > }
> > >
> > > -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > > - u32 link_clock, u32 lane_count,
> > > - u32 mode_clock, u32 mode_hdisplay,
> > > - bool bigjoiner,
> > > - u32 pipe_bpp)
> > > +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > > + u32 link_clock, u32 lane_count,
> > > + u32 mode_clock, u32 mode_hdisplay,
> > > + bool bigjoiner,
> > > + u32 pipe_bpp,
> > > + u32 timeslots)
> > > {
> > > u32 bits_per_pixel, max_bpp_small_joiner_ram;
> > > int i;
> > > @@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> > > drm_i915_private *i915,
> > > * for SST -> TimeSlotsPerMTP is 1,
> > > * for MST -> TimeSlotsPerMTP has to be calculated
> > > */
> > > - bits_per_pixel = (link_clock * lane_count * 8) /
> > > + bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
> > > intel_dp_mode_to_fec_clock(mode_clock);
> > > + drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
> > >
> > > /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz.
> > > width */
> > > max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
> > > @@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> > > drm_i915_private *i915,
> > > return bits_per_pixel << 4;
> > > }
> > >
> > > -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > > - int mode_clock, int mode_hdisplay,
> > > - bool bigjoiner)
> > > +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > > + int mode_clock, int mode_hdisplay,
> > > + bool bigjoiner)
> > > {
> > > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > u8 min_slice_count, i;
> > > @@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
> > > *connector,
> > > return MODE_OK;
> > > }
> > >
> > > -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> > > - int hdisplay, int clock)
> > > +bool intel_dp_need_bigjoiner(struct intel_dp
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
On Thu, Aug 25, 2022 at 05:58:19PM +0300, Govindapillai, Vinod wrote:
> Hi Stan,
>
> Some comments inline..
>
> On Mon, 2022-08-22 at 12:40 +0300, Stanislav Lisovskiy wrote:
> > Whenever we are not able to get enough timeslots
> > for required PBN, let's try to allocate those
> > using DSC, just same way as we do for SST.
> >
> > v2: Removed intel_dp_mst_dsc_compute_config and refactored
> > intel_dp_dsc_compute_config to support timeslots as a
> > parameter(Ville Syrjälä)
> >
> > v3: - Rebased
> > - Added a debug to see that we at least try reserving
> > VCPI slots using DSC, because currently its not visible
> > from the logs, thus making debugging more tricky.
> > - Moved timeslots to numerator, where it should be.
> >
> > v4: - Call drm_dp_mst_atomic_check already during link
> > config computation, because we need to know already
> > by this moment if uncompressed amount of VCPI slots
> > needed can fit, otherwise we need to use DSC.
> > (thanks to Vinod Govindapillai for pointing this out)
> >
> > v5: - Put pipe_config->bigjoiner_pipes back to original
> > condition in intel_dp_dsc_compute_config
> > (don't remember when I lost it)
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 73 -
> > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
> > 3 files changed, 205 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 32292c0be2bd..519b436fc530 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> > }
> >
> > static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> > -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
> > dsc_max_bpc);
> >
> > /* Is link rate UHBR and thus 128b/132b? */
> > bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> > @@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private
> > *i915)
> > return 6144 * 8;
> > }
> >
> > -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > - u32 link_clock, u32 lane_count,
> > - u32 mode_clock, u32 mode_hdisplay,
> > - bool bigjoiner,
> > - u32 pipe_bpp)
> > +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > + u32 link_clock, u32 lane_count,
> > + u32 mode_clock, u32 mode_hdisplay,
> > + bool bigjoiner,
> > + u32 pipe_bpp,
> > + u32 timeslots)
> > {
> > u32 bits_per_pixel, max_bpp_small_joiner_ram;
> > int i;
> > @@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> > drm_i915_private *i915,
> > * for SST -> TimeSlotsPerMTP is 1,
> > * for MST -> TimeSlotsPerMTP has to be calculated
> > */
> > - bits_per_pixel = (link_clock * lane_count * 8) /
> > + bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
> > intel_dp_mode_to_fec_clock(mode_clock);
> > + drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
> >
> > /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz.
> > width */
> > max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
> > @@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> > drm_i915_private *i915,
> > return bits_per_pixel << 4;
> > }
> >
> > -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > - int mode_clock, int mode_hdisplay,
> > - bool bigjoiner)
> > +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > + int mode_clock, int mode_hdisplay,
> > + bool bigjoiner)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > u8 min_slice_count, i;
> > @@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
> > *connector,
> > return MODE_OK;
> > }
> >
> > -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> > - int hdisplay, int clock)
> > +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> > + int hdisplay, int clock)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >
> > @@ -1049,7 +1050,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> >
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Hi Stan,
Some comments inline..
On Mon, 2022-08-22 at 12:40 +0300, Stanislav Lisovskiy wrote:
> Whenever we are not able to get enough timeslots
> for required PBN, let's try to allocate those
> using DSC, just same way as we do for SST.
>
> v2: Removed intel_dp_mst_dsc_compute_config and refactored
> intel_dp_dsc_compute_config to support timeslots as a
> parameter(Ville Syrjälä)
>
> v3: - Rebased
> - Added a debug to see that we at least try reserving
> VCPI slots using DSC, because currently its not visible
> from the logs, thus making debugging more tricky.
> - Moved timeslots to numerator, where it should be.
>
> v4: - Call drm_dp_mst_atomic_check already during link
> config computation, because we need to know already
> by this moment if uncompressed amount of VCPI slots
> needed can fit, otherwise we need to use DSC.
> (thanks to Vinod Govindapillai for pointing this out)
>
> v5: - Put pipe_config->bigjoiner_pipes back to original
> condition in intel_dp_dsc_compute_config
> (don't remember when I lost it)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 73 -
> drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
> 3 files changed, 205 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 32292c0be2bd..519b436fc530 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> }
>
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
> dsc_max_bpc);
>
> /* Is link rate UHBR and thus 128b/132b? */
> bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> @@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private
> *i915)
> return 6144 * 8;
> }
>
> -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> - u32 link_clock, u32 lane_count,
> - u32 mode_clock, u32 mode_hdisplay,
> - bool bigjoiner,
> - u32 pipe_bpp)
> +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> + u32 link_clock, u32 lane_count,
> + u32 mode_clock, u32 mode_hdisplay,
> + bool bigjoiner,
> + u32 pipe_bpp,
> + u32 timeslots)
> {
> u32 bits_per_pixel, max_bpp_small_joiner_ram;
> int i;
> @@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
> * for SST -> TimeSlotsPerMTP is 1,
> * for MST -> TimeSlotsPerMTP has to be calculated
> */
> - bits_per_pixel = (link_clock * lane_count * 8) /
> + bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
> intel_dp_mode_to_fec_clock(mode_clock);
> + drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
>
> /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width
> */
> max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
> @@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
> return bits_per_pixel << 4;
> }
>
> -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> - int mode_clock, int mode_hdisplay,
> - bool bigjoiner)
> +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> + int mode_clock, int mode_hdisplay,
> + bool bigjoiner)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> u8 min_slice_count, i;
> @@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
> *connector,
> return MODE_OK;
> }
>
> -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> - int hdisplay, int clock)
> +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> + int hdisplay, int clock)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> @@ -1049,7 +1050,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> target_clock,
> mode->hdisplay,
> bigjoiner,
> - pipe_bpp) >> 4;
> +
[Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
v3: - Rebased
- Added a debug to see that we at least try reserving
VCPI slots using DSC, because currently its not visible
from the logs, thus making debugging more tricky.
- Moved timeslots to numerator, where it should be.
v4: - Call drm_dp_mst_atomic_check already during link
config computation, because we need to know already
by this moment if uncompressed amount of VCPI slots
needed can fit, otherwise we need to use DSC.
(thanks to Vinod Govindapillai for pointing this out)
v5: - Put pipe_config->bigjoiner_pipes back to original
condition in intel_dp_dsc_compute_config
(don't remember when I lost it)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 -
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
3 files changed, 205 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..519b436fc530 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for SST -> TimeSlotsPerMTP is 1,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
- bits_per_pixel = (link_clock * lane_count * 8) /
+ bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
intel_dp_mode_to_fec_clock(mode_clock);
+ drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
@@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1049,7 +1050,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1354,7 +1355,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
[Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
v3: - Rebased
- Added a debug to see that we at least try reserving
VCPI slots using DSC, because currently its not visible
from the logs, thus making debugging more tricky.
- Moved timeslots to numerator, where it should be.
v4: - Call drm_dp_mst_atomic_check already during link
config computation, because we need to know already
by this moment if uncompressed amount of VCPI slots
needed can fit, otherwise we need to use DSC.
(thanks to Vinod Govindapillai for pointing this out)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 76 --
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
3 files changed, 206 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..1f6dc52251c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for SST -> TimeSlotsPerMTP is 1,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
- bits_per_pixel = (link_clock * lane_count * 8) /
+ bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
intel_dp_mode_to_fec_clock(mode_clock);
+ drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
@@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1049,7 +1050,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1354,7 +1355,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
On Wed, Aug 10, 2022 at 11:25:13AM +0300, Govindapillai, Vinod wrote:
> Hi Stan,
>
> Please find my comments inline
>
>
> On Mon, 2022-04-11 at 19:25 +0300, Stanislav Lisovskiy wrote:
> > Whenever we are not able to get enough timeslots
> > for required PBN, let's try to allocate those
> > using DSC, just same way as we do for SST.
> >
> > v2: Removed intel_dp_mst_dsc_compute_config and refactored
> > intel_dp_dsc_compute_config to support timeslots as a
> > parameter(Ville Syrjälä)
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
> > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 143
> > 3 files changed, 191 insertions(+), 44 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 972c9ed46829..f5477f1bf622 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -114,7 +114,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> > }
> >
> > static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> > -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
> > dsc_max_bpc);
> >
> > /* Is link rate UHBR and thus 128b/132b? */
> > bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> > @@ -640,11 +639,12 @@ small_joiner_ram_size_bits(struct drm_i915_private
> > *i915)
> > return 6144 * 8;
> > }
> >
> > -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > - u32 link_clock, u32 lane_count,
> > - u32 mode_clock, u32 mode_hdisplay,
> > - bool bigjoiner,
> > - u32 pipe_bpp)
> > +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > + u32 link_clock, u32 lane_count,
> > + u32 mode_clock, u32 mode_hdisplay,
> > + bool bigjoiner,
> > + u32 pipe_bpp,
> > + u32 timeslots)
> > {
> > u32 bits_per_pixel, max_bpp_small_joiner_ram;
> > int i;
> > @@ -656,7 +656,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> > drm_i915_private *i915,
> > * for MST -> TimeSlotsPerMTP has to be calculated
> > */
> > bits_per_pixel = (link_clock * lane_count * 8) /
> > -intel_dp_mode_to_fec_clock(mode_clock);
> > +(intel_dp_mode_to_fec_clock(mode_clock) * timeslots);
> > drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
> >
> > /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
> > @@ -710,9 +710,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> > drm_i915_private *i915,
> > return bits_per_pixel << 4;
> > }
> >
> > -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > - int mode_clock, int mode_hdisplay,
> > - bool bigjoiner)
> > +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > + int mode_clock, int mode_hdisplay,
> > + bool bigjoiner)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > u8 min_slice_count, i;
> > @@ -919,8 +919,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
> > *connector,
> > return MODE_OK;
> > }
> >
> > -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> > - int hdisplay, int clock)
> > +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> > +int hdisplay, int clock)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >
> > @@ -1007,7 +1007,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> > target_clock,
> > mode->hdisplay,
> > bigjoiner,
> > - pipe_bpp) >> 4;
> > + pipe_bpp, 1) >> 4;
> > dsc_slice_count =
> > intel_dp_dsc_get_slice_count(intel_dp,
> > target_clock,
> > @@ -1311,7 +1311,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
> > *intel_dp,
> > return -EINVAL;
> > }
> >
> > -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
> > max_req_bpc)
> > +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > int i, num_bpc;
> > @@ -1401,10 +1401,11 @@ static int
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Hi Stan,
Please find my comments inline
On Mon, 2022-04-11 at 19:25 +0300, Stanislav Lisovskiy wrote:
> Whenever we are not able to get enough timeslots
> for required PBN, let's try to allocate those
> using DSC, just same way as we do for SST.
>
> v2: Removed intel_dp_mst_dsc_compute_config and refactored
> intel_dp_dsc_compute_config to support timeslots as a
> parameter(Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
> drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 143
> 3 files changed, 191 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 972c9ed46829..f5477f1bf622 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -114,7 +114,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> }
>
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
> dsc_max_bpc);
>
> /* Is link rate UHBR and thus 128b/132b? */
> bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> @@ -640,11 +639,12 @@ small_joiner_ram_size_bits(struct drm_i915_private
> *i915)
> return 6144 * 8;
> }
>
> -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> -u32 link_clock, u32 lane_count,
> -u32 mode_clock, u32 mode_hdisplay,
> -bool bigjoiner,
> -u32 pipe_bpp)
> +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> + u32 link_clock, u32 lane_count,
> + u32 mode_clock, u32 mode_hdisplay,
> + bool bigjoiner,
> + u32 pipe_bpp,
> + u32 timeslots)
> {
> u32 bits_per_pixel, max_bpp_small_joiner_ram;
> int i;
> @@ -656,7 +656,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
>* for MST -> TimeSlotsPerMTP has to be calculated
>*/
> bits_per_pixel = (link_clock * lane_count * 8) /
> - intel_dp_mode_to_fec_clock(mode_clock);
> + (intel_dp_mode_to_fec_clock(mode_clock) * timeslots);
> drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
>
> /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
> @@ -710,9 +710,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
> return bits_per_pixel << 4;
> }
>
> -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> -int mode_clock, int mode_hdisplay,
> -bool bigjoiner)
> +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> + int mode_clock, int mode_hdisplay,
> + bool bigjoiner)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> u8 min_slice_count, i;
> @@ -919,8 +919,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
> *connector,
> return MODE_OK;
> }
>
> -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> - int hdisplay, int clock)
> +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> + int hdisplay, int clock)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> @@ -1007,7 +1007,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> target_clock,
> mode->hdisplay,
> bigjoiner,
> - pipe_bpp) >> 4;
> + pipe_bpp, 1) >> 4;
> dsc_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
>target_clock,
> @@ -1311,7 +1311,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
> *intel_dp,
> return -EINVAL;
> }
>
> -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
> max_req_bpc)
> +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> int i, num_bpc;
> @@ -1401,10 +1401,11 @@ static int intel_dp_dsc_compute_params(struct
> intel_encoder *encoder,
> return drm_dsc_compute_rc_parameters(vdsc_cfg);
> }
>
> -static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> -
[Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
v3: - Rebased
- Added a debug to see that we at least try reserving
VCPI slots using DSC, because currently its not visible
from the logs, thus making debugging more tricky.
- Moved timeslots to numerator, where it should be.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 76 +-
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 145
3 files changed, 194 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..1f6dc52251c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for SST -> TimeSlotsPerMTP is 1,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
- bits_per_pixel = (link_clock * lane_count * 8) /
+ bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
intel_dp_mode_to_fec_clock(mode_clock);
+ drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
@@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1049,7 +1050,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1354,7 +1355,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1444,10 +1445,11 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
return
[Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 143
3 files changed, 191 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 972c9ed46829..f5477f1bf622 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -114,7 +114,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -640,11 +639,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -656,7 +656,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
bits_per_pixel = (link_clock * lane_count * 8) /
-intel_dp_mode_to_fec_clock(mode_clock);
+(intel_dp_mode_to_fec_clock(mode_clock) * timeslots);
drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
@@ -710,9 +710,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -919,8 +919,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1007,7 +1007,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1311,7 +1311,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1401,10 +1401,11 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
-static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
- struct drm_connector_state *conn_state,
- struct link_config_limits *limits)
+int intel_dp_dsc_compute_config(struct
[Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 143
3 files changed, 191 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9e19165fd175..b8e1561b5eca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -115,7 +115,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -667,11 +666,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -683,7 +683,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
bits_per_pixel = (link_clock * lane_count * 8) /
-intel_dp_mode_to_fec_clock(mode_clock);
+(intel_dp_mode_to_fec_clock(mode_clock) * timeslots);
drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
@@ -737,9 +737,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -902,8 +902,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -990,7 +990,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1285,7 +1285,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1375,10 +1375,11 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
-static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
- struct drm_connector_state *conn_state,
- struct link_config_limits *limits)
+int intel_dp_dsc_compute_config(struct intel_dp
[Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Add DSC checks to intel_dp_mst_mode_valid_ctx, similar
to ones we have in intel_dp_mode_valid(Manasi Navare)
v3: Removed redundant edp condition logic from MST DSC
handling(Manasi Navare)
v4: - Fixed forgotten force_dsc_en condition which was
always enabled for testing purposes(Manasi Navare)
- Properly process ret == EDEADLK, thus fixing the
regression caused by WARN triggered with modeset_lock.
v5: - Removed redundant check(Imre Deak)
v6: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
Acked-by: Imre Deak
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 143
3 files changed, 191 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9e19165fd175..b8e1561b5eca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -115,7 +115,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -667,11 +666,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -683,7 +683,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
bits_per_pixel = (link_clock * lane_count * 8) /
-intel_dp_mode_to_fec_clock(mode_clock);
+(intel_dp_mode_to_fec_clock(mode_clock) * timeslots);
drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
@@ -737,9 +737,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -902,8 +902,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -990,7 +990,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1285,7 +1285,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
On Thu, Mar 17, 2022 at 06:52:28PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 17, 2022 at 06:33:53PM +0200, Stanislav Lisovskiy wrote:
> > Whenever we are not able to get enough timeslots
> > for required PBN, let's try to allocate those
> > using DSC, just same way as we do for SST.
> >
> > Those patches are experimental yet, i.e not
> > for merging, still need to be tested with
> > proper DSC display, submitting those to check
> > ig nothing else blows up at least.
> >
> > v2: Add DSC checks to intel_dp_mst_mode_valid_ctx, similar
> > to ones we have in intel_dp_mode_valid(Manasi Navare)
> >
> > v3: Removed redundant edp condition logic from MST DSC
> > handling(Manasi Navare)
> >
> > v4: - Fixed forgotten force_dsc_en condition which was
> >always enabled for testing purposes(Manasi Navare)
> > - Properly process ret == EDEADLK, thus fixing the
> >regression caused by WARN triggered with modeset_lock.
> >
> > v5: - Removed redundant check(Imre Deak)
> >
> > Acked-by: Imre Deak
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 138 --
> > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 146 +++-
> > 3 files changed, 285 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 9e19165fd175..b04771e495cc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -115,7 +115,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> > }
> >
> > static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> > -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
> > dsc_max_bpc);
> >
> > /* Is link rate UHBR and thus 128b/132b? */
> > bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> > @@ -667,11 +666,12 @@ small_joiner_ram_size_bits(struct drm_i915_private
> > *i915)
> > return 6144 * 8;
> > }
> >
> > -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > - u32 link_clock, u32 lane_count,
> > - u32 mode_clock, u32 mode_hdisplay,
> > - bool bigjoiner,
> > - u32 pipe_bpp)
> > +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > + u32 link_clock, u32 lane_count,
> > + u32 mode_clock, u32 mode_hdisplay,
> > + bool bigjoiner,
> > + u32 pipe_bpp,
> > + u32 timeslots)
> > {
> > u32 bits_per_pixel, max_bpp_small_joiner_ram;
> > int i;
> > @@ -683,7 +683,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> > drm_i915_private *i915,
> > * for MST -> TimeSlotsPerMTP has to be calculated
> > */
> > bits_per_pixel = (link_clock * lane_count * 8) /
> > -intel_dp_mode_to_fec_clock(mode_clock);
> > +(intel_dp_mode_to_fec_clock(mode_clock) * timeslots);
> > drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
> >
> > /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
> > @@ -737,9 +737,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> > drm_i915_private *i915,
> > return bits_per_pixel << 4;
> > }
> >
> > -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > - int mode_clock, int mode_hdisplay,
> > - bool bigjoiner)
> > +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > + int mode_clock, int mode_hdisplay,
> > + bool bigjoiner)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > u8 min_slice_count, i;
> > @@ -902,8 +902,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
> > *connector,
> > return MODE_OK;
> > }
> >
> > -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> > - int hdisplay, int clock)
> > +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> > +int hdisplay, int clock)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >
> > @@ -990,7 +990,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
> > target_clock,
> > mode->hdisplay,
> > bigjoiner,
> > - pipe_bpp) >> 4;
> > + pipe_bpp, 1) >> 4;
> > dsc_slice_count =
> >
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
On Thu, Mar 17, 2022 at 06:33:53PM +0200, Stanislav Lisovskiy wrote:
> Whenever we are not able to get enough timeslots
> for required PBN, let's try to allocate those
> using DSC, just same way as we do for SST.
>
> Those patches are experimental yet, i.e not
> for merging, still need to be tested with
> proper DSC display, submitting those to check
> ig nothing else blows up at least.
>
> v2: Add DSC checks to intel_dp_mst_mode_valid_ctx, similar
> to ones we have in intel_dp_mode_valid(Manasi Navare)
>
> v3: Removed redundant edp condition logic from MST DSC
> handling(Manasi Navare)
>
> v4: - Fixed forgotten force_dsc_en condition which was
>always enabled for testing purposes(Manasi Navare)
> - Properly process ret == EDEADLK, thus fixing the
>regression caused by WARN triggered with modeset_lock.
>
> v5: - Removed redundant check(Imre Deak)
>
> Acked-by: Imre Deak
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 138 --
> drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 146 +++-
> 3 files changed, 285 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9e19165fd175..b04771e495cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -115,7 +115,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> }
>
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
> dsc_max_bpc);
>
> /* Is link rate UHBR and thus 128b/132b? */
> bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> @@ -667,11 +666,12 @@ small_joiner_ram_size_bits(struct drm_i915_private
> *i915)
> return 6144 * 8;
> }
>
> -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> -u32 link_clock, u32 lane_count,
> -u32 mode_clock, u32 mode_hdisplay,
> -bool bigjoiner,
> -u32 pipe_bpp)
> +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> + u32 link_clock, u32 lane_count,
> + u32 mode_clock, u32 mode_hdisplay,
> + bool bigjoiner,
> + u32 pipe_bpp,
> + u32 timeslots)
> {
> u32 bits_per_pixel, max_bpp_small_joiner_ram;
> int i;
> @@ -683,7 +683,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
>* for MST -> TimeSlotsPerMTP has to be calculated
>*/
> bits_per_pixel = (link_clock * lane_count * 8) /
> - intel_dp_mode_to_fec_clock(mode_clock);
> + (intel_dp_mode_to_fec_clock(mode_clock) * timeslots);
> drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
>
> /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
> @@ -737,9 +737,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
> return bits_per_pixel << 4;
> }
>
> -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> -int mode_clock, int mode_hdisplay,
> -bool bigjoiner)
> +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> + int mode_clock, int mode_hdisplay,
> + bool bigjoiner)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> u8 min_slice_count, i;
> @@ -902,8 +902,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
> *connector,
> return MODE_OK;
> }
>
> -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> - int hdisplay, int clock)
> +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> + int hdisplay, int clock)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> @@ -990,7 +990,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
> target_clock,
> mode->hdisplay,
> bigjoiner,
> - pipe_bpp) >> 4;
> + pipe_bpp, 1) >> 4;
> dsc_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
>target_clock,
> @@ -1285,7 +1285,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
> *intel_dp,
> return -EINVAL;
> }
>
[Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
Those patches are experimental yet, i.e not
for merging, still need to be tested with
proper DSC display, submitting those to check
ig nothing else blows up at least.
v2: Add DSC checks to intel_dp_mst_mode_valid_ctx, similar
to ones we have in intel_dp_mode_valid(Manasi Navare)
v3: Removed redundant edp condition logic from MST DSC
handling(Manasi Navare)
v4: - Fixed forgotten force_dsc_en condition which was
always enabled for testing purposes(Manasi Navare)
- Properly process ret == EDEADLK, thus fixing the
regression caused by WARN triggered with modeset_lock.
v5: - Removed redundant check(Imre Deak)
Acked-by: Imre Deak
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 138 --
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 146 +++-
3 files changed, 285 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9e19165fd175..b04771e495cc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -115,7 +115,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -667,11 +666,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -683,7 +683,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
bits_per_pixel = (link_clock * lane_count * 8) /
-intel_dp_mode_to_fec_clock(mode_clock);
+(intel_dp_mode_to_fec_clock(mode_clock) * timeslots);
drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
@@ -737,9 +737,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -902,8 +902,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -990,7 +990,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1285,7 +1285,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 =
