Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix icl workarounds whitespaces

2018-11-14 Thread Mika Kuoppala 
Chris Wilson  writes:

> Quoting Mika Kuoppala (2018-11-09 14:53:33)
>> Align icl workarounds whitespace with the rest of the file
>> 
>> Cc: Chris Wilson 
>> Signed-off-by: Mika Kuoppala 
>
> That'll do. Fine piece of Wensleydale,
> Reviewed-by: Chris Wilson 

Both patches pushed, thanks for review.
-Mika
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix icl workarounds whitespaces

2018-11-09 Thread Chris Wilson 
Quoting Mika Kuoppala (2018-11-09 14:53:33)
> Align icl workarounds whitespace with the rest of the file
> 
> Cc: Chris Wilson 
> Signed-off-by: Mika Kuoppala 

That'll do. Fine piece of Wensleydale,
Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] [PATCH 2/2] drm/i915: Fix icl workarounds whitespaces

2018-11-09 Thread Mika Kuoppala 
Align icl workarounds whitespace with the rest of the file

Cc: Chris Wilson 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_workarounds.c | 27 ++--
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 406ba5bab063..ca1f78a42b17 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -823,18 +823,21 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
 
/* WaInPlaceDecompressionHang:icl */
-   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
-   
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 
/* WaPipelineFlushCoherentLines:icl */
-   I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
-  GEN8_LQSC_FLUSH_COHERENT_LINES);
+   I915_WRITE(GEN8_L3SQCREG4,
+  I915_READ(GEN8_L3SQCREG4) |
+  GEN8_LQSC_FLUSH_COHERENT_LINES);
 
/* Wa_1405543622:icl
 * Formerly known as WaGAPZPriorityScheme
 */
-   I915_WRITE(GEN8_GARBCNTL, I915_READ(GEN8_GARBCNTL) |
- GEN11_ARBITRATION_PRIO_ORDER_MASK);
+   I915_WRITE(GEN8_GARBCNTL,
+  I915_READ(GEN8_GARBCNTL) |
+  GEN11_ARBITRATION_PRIO_ORDER_MASK);
 
/* Wa_1604223664:icl
 * Formerly known as WaL3BankAddressHashing
@@ -854,15 +857,17 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
/* Wa_1405733216:icl
 * Formerly known as WaDisableCleanEvicts
 */
-   I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
-  GEN11_LQSC_CLEAN_EVICT_DISABLE);
+   I915_WRITE(GEN8_L3SQCREG4,
+  I915_READ(GEN8_L3SQCREG4) |
+  GEN11_LQSC_CLEAN_EVICT_DISABLE);
 
/* Wa_1405766107:icl
 * Formerly known as WaCL2SFHalfMaxAlloc
 */
-   I915_WRITE(GEN11_LSN_UNSLCVC, I915_READ(GEN11_LSN_UNSLCVC) |
- GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
- GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
+   I915_WRITE(GEN11_LSN_UNSLCVC,
+  I915_READ(GEN11_LSN_UNSLCVC) |
+  GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+  GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
 
/* Wa_220166154:icl
 * Formerly known as WaDisCtxReload
-- 
2.17.1

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