Re: [Intel-gfx] [PATCH 2/2] drm/i915: Sort DEV_INFO_FOR_EACH_FLAG

[Tvrtko Ursulin]

On 04/10/2016 14:32, Chris Wilson wrote:

On Tue, Oct 04, 2016 at 03:42:58PM +0300, Joonas Lahtinen wrote:

Sort DEV_INFO_FOR_EACH_FLAG to alphabetical order (except is_*).

Signed-off-by: Joonas Lahtinen 

Ok. Looks like it should be easier to read.
Reviewed-by: Chris Wilson 

Could you add something like:

/* Keep is_* in chronological order */

/* Keep has_* in alphabetical order */
...


You could also push is_mobile and is_preliminary to the end of the is_ 
block which would be a micro-opt for the "IS_SKYLAKE || IS_KABYLAKE" 
code and similar for the checks for the earlier hardware. If flags for 
things of similar age end up in the same byte then checking for compound 
conditions is shorter. :) As it stands they are just split across byte 
boundaries. :))


Regards,

Tvrtko

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Sort DEV_INFO_FOR_EACH_FLAG

[Chris Wilson]

On Tue, Oct 04, 2016 at 03:42:58PM +0300, Joonas Lahtinen wrote:
> Sort DEV_INFO_FOR_EACH_FLAG to alphabetical order (except is_*).
> 
> Signed-off-by: Joonas Lahtinen 

Ok. Looks like it should be easier to read.
Reviewed-by: Chris Wilson 

Could you add something like:

/* Keep is_* in chronological order */

/* Keep has_* in alphabetical order */
...
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH 2/2] drm/i915: Sort DEV_INFO_FOR_EACH_FLAG

[Joonas Lahtinen]

Sort DEV_INFO_FOR_EACH_FLAG to alphabetical order (except is_*).

Signed-off-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h | 36 ++--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f13b958..2ce1171 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -640,7 +640,6 @@ struct intel_csr {
func(is_i915g) \
func(is_i945gm) \
func(is_g33) \
-   func(hws_needs_physical) \
func(is_g4x) \
func(is_pineview) \
func(is_broadwater) \
@@ -654,31 +653,32 @@ struct intel_csr {
func(is_broxton) \
func(is_kabylake) \
func(is_preliminary) \
-   func(has_fbc) \
-   func(has_psr) \
-   func(has_runtime_pm) \
func(has_csr) \
-   func(has_resource_streamer) \
-   func(has_rc6) \
-   func(has_rc6p) \
+   func(has_ddi) \
func(has_dp_mst) \
+   func(has_fbc) \
+   func(has_fpga_dbg) \
func(has_gmbus_irq) \
-   func(has_hw_contexts) \
-   func(has_logical_ring_contexts) \
-   func(has_l3_dpf) \
func(has_gmch_display) \
func(has_guc) \
-   func(has_pipe_cxsr) \
func(has_hotplug) \
-   func(cursor_needs_physical) \
-   func(has_overlay) \
-   func(overlay_needs_physical) \
-   func(supports_tv) \
+   func(has_hw_contexts) \
+   func(has_l3_dpf) \
func(has_llc) \
+   func(has_logical_ring_contexts) \
+   func(has_overlay) \
+   func(has_pipe_cxsr) \
+   func(has_pooled_eu) \
+   func(has_psr) \
+   func(has_rc6) \
+   func(has_rc6p) \
+   func(has_resource_streamer) \
+   func(has_runtime_pm) \
func(has_snoop) \
-   func(has_ddi) \
-   func(has_fpga_dbg) \
-   func(has_pooled_eu)
+   func(hws_needs_physical) \
+   func(cursor_needs_physical) \
+   func(overlay_needs_physical) \
+   func(supports_tv)
 
 struct sseu_dev_info {
u8 slice_mask;
-- 
2.7.4

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