[Intel-gfx] [PATCH 2/3] drm/i915/dg2: Add initial gt/ctx/engine workarounds

2021-11-02 Thread Matt Roper 
Bspec: 54077,68173,54833
Cc: Anusha Srivatsa 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 278 +++-
 drivers/gpu/drm/i915/i915_reg.h |  94 +--
 drivers/gpu/drm/i915/intel_pm.c |  21 +-
 3 files changed, 372 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4aaa210fc003..37fd541a9719 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -644,6 +644,42 @@ static void dg1_ctx_workarounds_init(struct 
intel_engine_cs *engine,
 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
 }
 
+static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
+struct i915_wa_list *wal)
+{
+   gen12_ctx_gt_tuning_init(engine, wal);
+
+   /* Wa_16011186671:dg2_g11 */
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
+   wa_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH);
+   wa_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE);
+   }
+
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
+   /* Wa_14010469329:dg2_g10 */
+   wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
+XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
+
+   /*
+* Wa_22010465075:dg2_g10
+* Wa_22010613112:dg2_g10
+* Wa_14010698770:dg2_g10
+*/
+   wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
+GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+   }
+
+   /* Wa_16013271637:dg2 */
+   wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
+MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
+
+   /* Wa_22012532006:dg2 */
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) ||
+   IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
+   wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
+DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
+}
+
 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
 struct i915_wa_list *wal)
 {
@@ -730,7 +766,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
if (engine->class != RENDER_CLASS)
goto done;
 
-   if (IS_XEHPSDV(i915))
+   if (IS_DG2(i915))
+   dg2_ctx_workarounds_init(engine, wal);
+   else if (IS_XEHPSDV(i915))
; /* noop; none at this time */
else if (IS_DG1(i915))
dg1_ctx_workarounds_init(engine, wal);
@@ -1343,12 +1381,117 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, 
struct i915_wa_list *wal)
GLOBAL_INVALIDATION_MODE);
 }
 
+static void
+dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
+{
+   struct intel_engine_cs *engine;
+   int id;
+
+   xehp_init_mcr(gt, wal);
+
+   /* Wa_14011060649:dg2 */
+   wa_14011060649(gt, wal);
+
+   /*
+* Although there are per-engine instances of these registers,
+* they technically exist outside the engine itself and are not
+* impacted by engine resets.  Furthermore, they're part of the
+* GuC blacklist so trying to treat them as engine workarounds
+* will result in GuC initialization failure and a wedged GPU.
+*/
+   for_each_engine(engine, gt, id) {
+   if (engine->class != VIDEO_DECODE_CLASS)
+   continue;
+
+   /* Wa_16010515920:dg2_g10 */
+   if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
+   wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base),
+   ALNUNIT_CLKGATE_DIS);
+   }
+
+   if (IS_DG2_G10(gt->i915)) {
+   /* Wa_22010523718:dg2 */
+   wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
+   CG3DDISCFEG_CLKGATE_DIS);
+
+   /* Wa_14011006942:dg2 */
+   wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE,
+   DSS_ROUTER_CLKGATE_DIS);
+   }
+
+   if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) {
+   /* Wa_14010680813:dg2_g10 */
+   wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS |
+   EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS);
+
+   /* Wa_14010948348:dg2_g10 */
+   wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS);
+
+   /* Wa_14011037102:dg2_g10 */
+   wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
+
+   /* Wa_14011371254:dg2_g10 */
+   wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
+
+   /* Wa_14011431319:dg2_g10 */
+   w

Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: Add initial gt/ctx/engine workarounds

2021-11-03 Thread Srivatsa, Anusha 



> -Original Message-
> From: Roper, Matthew D 
> Sent: Tuesday, November 2, 2021 3:25 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Roper, Matthew D
> ; Srivatsa, Anusha
> 
> Subject: [PATCH 2/3] drm/i915/dg2: Add initial gt/ctx/engine workarounds
> 
> Bspec: 54077,68173,54833
> Cc: Anusha Srivatsa 
> Signed-off-by: Matt Roper 

Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 278 +++-
>  drivers/gpu/drm/i915/i915_reg.h |  94 +--
>  drivers/gpu/drm/i915/intel_pm.c |  21 +-
>  3 files changed, 372 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4aaa210fc003..37fd541a9719 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -644,6 +644,42 @@ static void dg1_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
>  }
> 
> +static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> +  struct i915_wa_list *wal)
> +{
> + gen12_ctx_gt_tuning_init(engine, wal);
> +
> + /* Wa_16011186671:dg2_g11 */
> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
> + wa_masked_dis(wal, VFLSKPD,
> DIS_MULT_MISS_RD_SQUASH);
> + wa_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE);
> + }
> +
> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
> + /* Wa_14010469329:dg2_g10 */
> + wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> +  XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
> +
> + /*
> +  * Wa_22010465075:dg2_g10
> +  * Wa_22010613112:dg2_g10
> +  * Wa_14010698770:dg2_g10
> +  */
> + wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> +  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> + }
> +
> + /* Wa_16013271637:dg2 */
> + wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
> +  MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
> +
> + /* Wa_22012532006:dg2 */
> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) ||
> + IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
> + wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
> +
> DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
> +}
> +
>  static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
>struct i915_wa_list *wal)
>  {
> @@ -730,7 +766,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs
> *engine,
>   if (engine->class != RENDER_CLASS)
>   goto done;
> 
> - if (IS_XEHPSDV(i915))
> + if (IS_DG2(i915))
> + dg2_ctx_workarounds_init(engine, wal);
> + else if (IS_XEHPSDV(i915))
>   ; /* noop; none at this time */
>   else if (IS_DG1(i915))
>   dg1_ctx_workarounds_init(engine, wal); @@ -1343,12
> +1381,117 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
>   GLOBAL_INVALIDATION_MODE);
>  }
> 
> +static void
> +dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> +{
> + struct intel_engine_cs *engine;
> + int id;
> +
> + xehp_init_mcr(gt, wal);
> +
> + /* Wa_14011060649:dg2 */
> + wa_14011060649(gt, wal);
> +
> + /*
> +  * Although there are per-engine instances of these registers,
> +  * they technically exist outside the engine itself and are not
> +  * impacted by engine resets.  Furthermore, they're part of the
> +  * GuC blacklist so trying to treat them as engine workarounds
> +  * will result in GuC initialization failure and a wedged GPU.
> +  */
> + for_each_engine(engine, gt, id) {
> + if (engine->class != VIDEO_DECODE_CLASS)
> + continue;
> +
> + /* Wa_16010515920:dg2_g10 */
> + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0,
> STEP_B0))
> + wa_write_or(wal, VDBOX_CGCTL3F18(engine-
> >mmio_base),
> + ALNUNIT_CLKGATE_DIS);
> + }
> +
> + if (IS_DG2_G10(gt->i915)) {
> + /* Wa_22010523718:dg2 */
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
> + CG3DDISCFEG_CLKGATE_DIS);
> +
> + /* Wa_14011006942:dg2 */
> + wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE,
> + DSS_ROUTER_CLKGATE_DIS);
> + }
> +
> + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) {
> + /* Wa_14010680813:dg2_g10 */
> + wa_write_or(wal, GEN12_GAMSTLB_CTRL,
> CONTROL_BLOCK_CLKGATE_DIS |
> + EGRESS_BLOCK_CLKGATE_DIS |
> TAG_BLOCK_CLKGATE_DIS);
> +
> + /*

Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: Add initial gt/ctx/engine workarounds

2021-11-12 Thread Petri Latvala 
On Tue, Nov 02, 2021 at 03:25:10PM -0700, Matt Roper wrote:
> Bspec: 54077,68173,54833
> Cc: Anusha Srivatsa 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 278 +++-
>  drivers/gpu/drm/i915/i915_reg.h |  94 +--
>  drivers/gpu/drm/i915/intel_pm.c |  21 +-
>  3 files changed, 372 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4aaa210fc003..37fd541a9719 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -644,6 +644,42 @@ static void dg1_ctx_workarounds_init(struct 
> intel_engine_cs *engine,
>DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
>  }
>  
> +static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> +  struct i915_wa_list *wal)
> +{
> + gen12_ctx_gt_tuning_init(engine, wal);
> +
> + /* Wa_16011186671:dg2_g11 */
> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
> + wa_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH);
> + wa_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE);
> + }
> +
> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
> + /* Wa_14010469329:dg2_g10 */
> + wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> +  XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
> +
> + /*
> +  * Wa_22010465075:dg2_g10
> +  * Wa_22010613112:dg2_g10
> +  * Wa_14010698770:dg2_g10
> +  */
> + wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> +  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> + }
> +
> + /* Wa_16013271637:dg2 */
> + wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
> +  MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
> +
> + /* Wa_22012532006:dg2 */
> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) ||
> + IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
> + wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
> +  DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
> +}
> +
>  static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
>struct i915_wa_list *wal)
>  {
> @@ -730,7 +766,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>   if (engine->class != RENDER_CLASS)
>   goto done;
>  
> - if (IS_XEHPSDV(i915))
> + if (IS_DG2(i915))
> + dg2_ctx_workarounds_init(engine, wal);
> + else if (IS_XEHPSDV(i915))
>   ; /* noop; none at this time */
>   else if (IS_DG1(i915))
>   dg1_ctx_workarounds_init(engine, wal);
> @@ -1343,12 +1381,117 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, 
> struct i915_wa_list *wal)
>   GLOBAL_INVALIDATION_MODE);
>  }
>  
> +static void
> +dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> +{
> + struct intel_engine_cs *engine;
> + int id;
> +
> + xehp_init_mcr(gt, wal);
> +
> + /* Wa_14011060649:dg2 */
> + wa_14011060649(gt, wal);
> +
> + /*
> +  * Although there are per-engine instances of these registers,
> +  * they technically exist outside the engine itself and are not
> +  * impacted by engine resets.  Furthermore, they're part of the
> +  * GuC blacklist so trying to treat them as engine workarounds
> +  * will result in GuC initialization failure and a wedged GPU.
> +  */
> + for_each_engine(engine, gt, id) {
> + if (engine->class != VIDEO_DECODE_CLASS)
> + continue;
> +
> + /* Wa_16010515920:dg2_g10 */
> + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
> + wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base),
> + ALNUNIT_CLKGATE_DIS);
> + }
> +
> + if (IS_DG2_G10(gt->i915)) {
> + /* Wa_22010523718:dg2 */
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
> + CG3DDISCFEG_CLKGATE_DIS);
> +
> + /* Wa_14011006942:dg2 */
> + wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE,
> + DSS_ROUTER_CLKGATE_DIS);
> + }
> +
> + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) {
> + /* Wa_14010680813:dg2_g10 */
> + wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS |
> + EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS);
> +
> + /* Wa_14010948348:dg2_g10 */
> + wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS);
> +
> + /* Wa_14011037102:dg2_g10 */
> + wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
> +
> + /* Wa_14011371254:

Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: Add initial gt/ctx/engine workarounds

2021-11-12 Thread Sarvela, Tomi P 
This issue was not catched by CI, because of series of unfortunate events.

Before, CI has rebooted without module blocklist, and CI catched boot-time
dmesg correctly and marked it as 'ci@boot' test with failure if there was a 
taint.

I've been doing changes to make blocklisting i915 possible and load it as
the first test of IGT: that'd make possible to remove some workarounds
and integrate the result better on our framework.

The test to decide if i915 should be modprobed was slightly off, and
on these runs where i915 failed to load in boot, it was modprobed again,
and modprobe hanged because of existing i915. Results were not collected.

I've added the condition to the conditional modprobe, and the results
from failed boot-time modprobe should be soon available as before,
eg. CI_DRM_10873 later shards with SNB.

Regards,

Tomi

> From: Latvala, Petri 
> On Tue, Nov 02, 2021 at 03:25:10PM -0700, Matt Roper wrote:
> > Bspec: 54077,68173,54833
> > Cc: Anusha Srivatsa 
> > Signed-off-by: Matt Roper 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 278
> +++-
> >  drivers/gpu/drm/i915/i915_reg.h |  94 +--
> >  drivers/gpu/drm/i915/intel_pm.c |  21 +-
> >  3 files changed, 372 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 4aaa210fc003..37fd541a9719 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -644,6 +644,42 @@ static void dg1_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> >
> DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
> >  }
> >
> > +static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> > +struct
> i915_wa_list *wal)
> > +{
> > +   gen12_ctx_gt_tuning_init(engine, wal);
> > +
> > +   /* Wa_16011186671:dg2_g11 */
> > +   if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0,
> STEP_B0)) {
> > +   wa_masked_dis(wal, VFLSKPD,
> DIS_MULT_MISS_RD_SQUASH);
> > +   wa_masked_en(wal, VFLSKPD,
> DIS_OVER_FETCH_CACHE);
> > +   }
> > +
> > +   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0,
> STEP_B0)) {
> > +   /* Wa_14010469329:dg2_g10 */
> > +   wa_masked_en(wal,
> GEN11_COMMON_SLICE_CHICKEN3,
> > +
> XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
> > +
> > +   /*
> > +* Wa_22010465075:dg2_g10
> > +* Wa_22010613112:dg2_g10
> > +* Wa_14010698770:dg2_g10
> > +*/
> > +   wa_masked_en(wal,
> GEN11_COMMON_SLICE_CHICKEN3,
> > +
> GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > +   }
> > +
> > +   /* Wa_16013271637:dg2 */
> > +   wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
> > +
> MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
> > +
> > +   /* Wa_22012532006:dg2 */
> > +   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0,
> STEP_C0) ||
> > +   IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0,
> STEP_B0))
> > +   wa_masked_en(wal,
> GEN9_HALF_SLICE_CHICKEN7,
> > +
> DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
> > +}
> > +
> >  static void fakewa_disable_nestedbb_mode(struct intel_engine_cs
> *engine,
> >
> struct i915_wa_list *wal)
> >  {
> > @@ -730,7 +766,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs
> *engine,
> > if (engine->class != RENDER_CLASS)
> > goto done;
> >
> > -   if (IS_XEHPSDV(i915))
> > +   if (IS_DG2(i915))
> > +   dg2_ctx_workarounds_init(engine, wal);
> > +   else if (IS_XEHPSDV(i915))
> > ; /* noop; none at this time */
> > else if (IS_DG1(i915))
> > dg1_ctx_workarounds_init(engine, wal);
> > @@ -1343,12 +1381,117 @@ xehpsdv_gt_workarounds_init(struct intel_gt
> *gt, struct i915_wa_list *wal)
> > GLOBAL_INVALIDATION_MODE);
> >  }
> >
> > +static void
> > +dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > +{
> > +   struct intel_engine_cs *engine;
> > +   int id;
> > +
> > +   xehp_init_mcr(gt, wal);
> > +
> > +   /* Wa_14011060649:dg2 */
> > +   wa_14011060649(gt, wal);
> > +
> > +   /*
> > +* Although there are per-engine instances of these registers,
> > +* they technically exist outside the engine itself and are not
> > +* impacted by engine resets.  Furthermore, they're part of the
> > +* GuC blacklist so trying to treat them as engine workarounds
> > +* will result in GuC initialization failure and a wedged GPU.
> > +*/
> > +   for_each_engine(engine, gt, id) {
> > +   if (engine->class != VIDEO_DECODE_CLASS)
> > +   continue;
> > +
> > +   /* Wa_16010515920:dg2_g10 */
> > +   if (IS_DG2_GRAPHICS_STEP(gt->i915, G10,
> STEP_A0, STEP_B0))
> > +   wa_write_or(wal,
> VDBOX_CGCTL3F18(engine->mmio_base),
> > +
> ALNUNIT_CLKGATE_DIS);
> > +   }
> > +
> > +   if (IS_DG2_G10(gt->i915)) {
> > +   /* Wa_22010523718:dg2 */
> > +   wa_writ