[Intel-gfx] [PATCH 2/4] drm/i915: fix Haswell FDI link training code
From: Paulo Zanoni This commit makes hsw_fdi_link_train responsible for implementing everything described in the "Enable and train FDI" section from the Hawell CRT mode set sequence documentation. We completely rewrite hsw_fdi_link_train to match the documentation and we also call it in the right place. This patch was initially sent as a series of tiny patches fixing every little problem of the function, but since there were too many patches fixing the same function it got a little difficult to get the "big picture" of how the function would be in the end, so here we amended all the patches into a single big patch fixing the whole function. Problems we fixed: 1 - Train Haswell FDI at the right time. We need to train the FDI before enabling the pipes and planes, so we're moving the call from lpt_pch_enable to haswell_crtc_enable directly. We are also removing ironlake_fdi_pll_enable since the PLL enablement on Haswell is completely different and is also done during the link training steps. 2 - Use the right FDI_RX_CTL register on Haswell There is only one PCH transcoder, so it's always _FDI_RXA_CTL. Using "pipe" here is wrong. 3 - Don't rely on DDI_BUF_CTL previous values Just set the bits we want, everything else is zero. Also POSTING_READ the register before sleeping. 4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train According to the mode set sequence documentation, this is the right place. According to the FDI_RX_TUSIZE register description, this is the value we should set. Also remove the code that sets this register from the old location: lpt_pch_enable. 5 - Properly program FDI_RX_MISC pwrdn lane values on HSW 6 - Wait only 35us for the FDI link training First we wait 30us for the FDI receiver lane calibration, then we wait 5us for the FDI auto training time. 7 - Remove an useless indentation level on hsw_fdi_link_train We already "break" when the link training succeeds. 8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE When we fail the training. 9 - Change Haswell FDI link training error messages We shouldn't call DRM_ERROR when still looping through voltage levels since this is expected and not really a failure. So in this commit we adjust the error path to only DRM_ERROR when we really fail after trying everything. While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since it's what we use everywhere. 10 - Try each voltage twice at hsw_fdi_link_train Now with Daniel Vetter's suggestion to use "/2" instead of ">>1". Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 17 -- drivers/gpu/drm/i915/intel_ddi.c | 108 +-- drivers/gpu/drm/i915/intel_display.c | 11 +--- 3 files changed, 76 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3674891..5e820fa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3936,16 +3936,21 @@ #define FDI_PORT_WIDTH_2X_LPT (1<<19) #define FDI_PORT_WIDTH_1X_LPT (0<<19) -#define _FDI_RXA_MISC0xf0010 -#define _FDI_RXB_MISC0xf1010 +#define _FDI_RXA_MISC 0xf0010 +#define _FDI_RXB_MISC 0xf1010 +#define FDI_RX_PWRDN_LANE1_MASK (3<<26) +#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) +#define FDI_RX_PWRDN_LANE0_MASK (3<<24) +#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) +#define FDI_RX_TP1_TO_TP2_48 (2<<20) +#define FDI_RX_TP1_TO_TP2_64 (3<<20) +#define FDI_RX_FDI_DELAY_90 (0x90<<0) +#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) + #define _FDI_RXA_TUSIZE1 0xf0030 #define _FDI_RXA_TUSIZE2 0xf0038 #define _FDI_RXB_TUSIZE1 0xf1030 #define _FDI_RXB_TUSIZE2 0xf1038 -#define FDI_RX_TP1_TO_TP2_48 (2<<20) -#define FDI_RX_TP1_TO_TP2_64 (3<<20) -#define FDI_RX_FDI_DELAY_90 (0x90<<0) -#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a7a555f..92c2d61 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -153,11 +153,33 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - int pipe = intel_crtc->pipe; - u32 reg, temp, i; + u32 temp, i, rx_ctl_val; + + /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the +* mode set "sequence for CRT port" document: +* -
Re: [Intel-gfx] [PATCH 2/4] drm/i915: fix Haswell FDI link training code
This is wrong Ignore it. I messed up rebasing it against the new patches. 2012/11/1 Paulo Zanoni : > From: Paulo Zanoni > > This commit makes hsw_fdi_link_train responsible for implementing > everything described in the "Enable and train FDI" section from the > Hawell CRT mode set sequence documentation. We completely rewrite > hsw_fdi_link_train to match the documentation and we also call it in > the right place. > > This patch was initially sent as a series of tiny patches fixing every > little problem of the function, but since there were too many patches > fixing the same function it got a little difficult to get the "big > picture" of how the function would be in the end, so here we amended > all the patches into a single big patch fixing the whole function. > > Problems we fixed: > > 1 - Train Haswell FDI at the right time. > > We need to train the FDI before enabling the pipes and planes, so > we're moving the call from lpt_pch_enable to haswell_crtc_enable > directly. > > We are also removing ironlake_fdi_pll_enable since the PLL > enablement on Haswell is completely different and is also done > during the link training steps. > > 2 - Use the right FDI_RX_CTL register on Haswell > > There is only one PCH transcoder, so it's always _FDI_RXA_CTL. > Using "pipe" here is wrong. > > 3 - Don't rely on DDI_BUF_CTL previous values > > Just set the bits we want, everything else is zero. Also > POSTING_READ the register before sleeping. > > 4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train > > According to the mode set sequence documentation, this is the > right place. According to the FDI_RX_TUSIZE register description, > this is the value we should set. > > Also remove the code that sets this register from the old > location: lpt_pch_enable. > > 5 - Properly program FDI_RX_MISC pwrdn lane values on HSW > > 6 - Wait only 35us for the FDI link training > > First we wait 30us for the FDI receiver lane calibration, then we > wait 5us for the FDI auto training time. > > 7 - Remove an useless indentation level on hsw_fdi_link_train > > We already "break" when the link training succeeds. > > 8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE > > When we fail the training. > > 9 - Change Haswell FDI link training error messages > > We shouldn't call DRM_ERROR when still looping through voltage > levels since this is expected and not really a failure. So in this > commit we adjust the error path to only DRM_ERROR when we really > fail after trying everything. > > While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since > it's what we use everywhere. > > 10 - Try each voltage twice at hsw_fdi_link_train > > Now with Daniel Vetter's suggestion to use "/2" instead of ">>1". > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_reg.h | 17 -- > drivers/gpu/drm/i915/intel_ddi.c | 108 > +-- > drivers/gpu/drm/i915/intel_display.c | 11 +--- > 3 files changed, 76 insertions(+), 60 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d4520d5..a167d76 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3924,16 +3924,21 @@ > #define FDI_PORT_WIDTH_2X_LPT (1<<19) > #define FDI_PORT_WIDTH_1X_LPT (0<<19) > > -#define _FDI_RXA_MISC0xf0010 > -#define _FDI_RXB_MISC0xf1010 > +#define _FDI_RXA_MISC 0xf0010 > +#define _FDI_RXB_MISC 0xf1010 > +#define FDI_RX_PWRDN_LANE1_MASK (3<<26) > +#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) > +#define FDI_RX_PWRDN_LANE0_MASK (3<<24) > +#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) > +#define FDI_RX_TP1_TO_TP2_48 (2<<20) > +#define FDI_RX_TP1_TO_TP2_64 (3<<20) > +#define FDI_RX_FDI_DELAY_90 (0x90<<0) > +#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) > + > #define _FDI_RXA_TUSIZE1 0xf0030 > #define _FDI_RXA_TUSIZE2 0xf0038 > #define _FDI_RXB_TUSIZE1 0xf1030 > #define _FDI_RXB_TUSIZE2 0xf1038 > -#define FDI_RX_TP1_TO_TP2_48 (2<<20) > -#define FDI_RX_TP1_TO_TP2_64 (3<<20) > -#define FDI_RX_FDI_DELAY_90 (0x90<<0) > -#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) > #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) > #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index a7a555f..92c2d61 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -153,11 +153,33 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = dev
[Intel-gfx] [PATCH 2/4] drm/i915: fix Haswell FDI link training code
From: Paulo Zanoni This commit makes hsw_fdi_link_train responsible for implementing everything described in the "Enable and train FDI" section from the Hawell CRT mode set sequence documentation. We completely rewrite hsw_fdi_link_train to match the documentation and we also call it in the right place. This patch was initially sent as a series of tiny patches fixing every little problem of the function, but since there were too many patches fixing the same function it got a little difficult to get the "big picture" of how the function would be in the end, so here we amended all the patches into a single big patch fixing the whole function. Problems we fixed: 1 - Train Haswell FDI at the right time. We need to train the FDI before enabling the pipes and planes, so we're moving the call from lpt_pch_enable to haswell_crtc_enable directly. We are also removing ironlake_fdi_pll_enable since the PLL enablement on Haswell is completely different and is also done during the link training steps. 2 - Use the right FDI_RX_CTL register on Haswell There is only one PCH transcoder, so it's always _FDI_RXA_CTL. Using "pipe" here is wrong. 3 - Don't rely on DDI_BUF_CTL previous values Just set the bits we want, everything else is zero. Also POSTING_READ the register before sleeping. 4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train According to the mode set sequence documentation, this is the right place. According to the FDI_RX_TUSIZE register description, this is the value we should set. Also remove the code that sets this register from the old location: lpt_pch_enable. 5 - Properly program FDI_RX_MISC pwrdn lane values on HSW 6 - Wait only 35us for the FDI link training First we wait 30us for the FDI receiver lane calibration, then we wait 5us for the FDI auto training time. 7 - Remove an useless indentation level on hsw_fdi_link_train We already "break" when the link training succeeds. 8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE When we fail the training. 9 - Change Haswell FDI link training error messages We shouldn't call DRM_ERROR when still looping through voltage levels since this is expected and not really a failure. So in this commit we adjust the error path to only DRM_ERROR when we really fail after trying everything. While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since it's what we use everywhere. 10 - Try each voltage twice at hsw_fdi_link_train Now with Daniel Vetter's suggestion to use "/2" instead of ">>1". Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 17 -- drivers/gpu/drm/i915/intel_ddi.c | 108 +-- drivers/gpu/drm/i915/intel_display.c | 11 +--- 3 files changed, 76 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d4520d5..a167d76 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3924,16 +3924,21 @@ #define FDI_PORT_WIDTH_2X_LPT (1<<19) #define FDI_PORT_WIDTH_1X_LPT (0<<19) -#define _FDI_RXA_MISC0xf0010 -#define _FDI_RXB_MISC0xf1010 +#define _FDI_RXA_MISC 0xf0010 +#define _FDI_RXB_MISC 0xf1010 +#define FDI_RX_PWRDN_LANE1_MASK (3<<26) +#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) +#define FDI_RX_PWRDN_LANE0_MASK (3<<24) +#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) +#define FDI_RX_TP1_TO_TP2_48 (2<<20) +#define FDI_RX_TP1_TO_TP2_64 (3<<20) +#define FDI_RX_FDI_DELAY_90 (0x90<<0) +#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) + #define _FDI_RXA_TUSIZE1 0xf0030 #define _FDI_RXA_TUSIZE2 0xf0038 #define _FDI_RXB_TUSIZE1 0xf1030 #define _FDI_RXB_TUSIZE2 0xf1038 -#define FDI_RX_TP1_TO_TP2_48 (2<<20) -#define FDI_RX_TP1_TO_TP2_64 (3<<20) -#define FDI_RX_FDI_DELAY_90 (0x90<<0) -#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a7a555f..92c2d61 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -153,11 +153,33 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - int pipe = intel_crtc->pipe; - u32 reg, temp, i; + u32 temp, i, rx_ctl_val; + + /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the +* mode set "sequence for CRT port" document: +* -
