subject:"\[Intel\-gfx\] \[PATCH 25\/43\] drm\/i915\: Include gpio_mmio

Re: [Intel-gfx] [PATCH 25/43] drm/i915: Include gpio_mmio_base in GMBUS reg defines

2015-10-12 Thread Jesse Barnes

On 09/18/2015 10:03 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 12 -
>  drivers/gpu/drm/i915/intel_i2c.c | 54 
> +---
>  2 files changed, 29 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b35e24f..0216771 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2114,7 +2114,7 @@ enum skl_disp_power_wells {
>  # define GPIO_DATA_VAL_IN(1 << 12)
>  # define GPIO_DATA_PULLUP_DISABLE(1 << 13)
>  
> -#define GMBUS0   0x5100 /* clock/port select */
> +#define GMBUS0   (dev_priv->gpio_mmio_base + 0x5100) /* 
> clock/port select */
>  #define   GMBUS_RATE_100KHZ  (0<<8)
>  #define   GMBUS_RATE_50KHZ   (1<<8)
>  #define   GMBUS_RATE_400KHZ  (2<<8) /* reserved on Pineview */
> @@ -2133,7 +2133,7 @@ enum skl_disp_power_wells {
>  #define   GMBUS_PIN_2_BXT2
>  #define   GMBUS_PIN_3_BXT3
>  #define   GMBUS_NUM_PINS 7 /* including 0 */
> -#define GMBUS1   0x5104 /* command/status */
> +#define GMBUS1   (dev_priv->gpio_mmio_base + 0x5104) /* 
> command/status */
>  #define   GMBUS_SW_CLR_INT   (1<<31)
>  #define   GMBUS_SW_RDY   (1<<30)
>  #define   GMBUS_ENT  (1<<29) /* enable timeout */
> @@ -2147,7 +2147,7 @@ enum skl_disp_power_wells {
>  #define   GMBUS_SLAVE_ADDR_SHIFT 1
>  #define   GMBUS_SLAVE_READ   (1<<0)
>  #define   GMBUS_SLAVE_WRITE  (0<<0)
> -#define GMBUS2   0x5108 /* status */
> +#define GMBUS2   (dev_priv->gpio_mmio_base + 0x5108) /* 
> status */
>  #define   GMBUS_INUSE(1<<15)
>  #define   GMBUS_HW_WAIT_PHASE(1<<14)
>  #define   GMBUS_STALL_TIMEOUT(1<<13)
> @@ -2155,14 +2155,14 @@ enum skl_disp_power_wells {
>  #define   GMBUS_HW_RDY   (1<<11)
>  #define   GMBUS_SATOER   (1<<10)
>  #define   GMBUS_ACTIVE   (1<<9)
> -#define GMBUS3   0x510c /* data buffer bytes 3-0 */
> -#define GMBUS4   0x5110 /* interrupt mask (Pineview+) */
> +#define GMBUS3   (dev_priv->gpio_mmio_base + 0x510c) /* 
> data buffer bytes 3-0 */
> +#define GMBUS4   (dev_priv->gpio_mmio_base + 0x5110) /* 
> interrupt mask (Pineview+) */
>  #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
>  #define   GMBUS_NAK_EN   (1<<3)
>  #define   GMBUS_IDLE_EN  (1<<2)
>  #define   GMBUS_HW_WAIT_EN   (1<<1)
>  #define   GMBUS_HW_RDY_EN(1<<0)
> -#define GMBUS5   0x5120 /* byte index */
> +#define GMBUS5   (dev_priv->gpio_mmio_base + 0x5120) /* 
> byte index */
>  #define   GMBUS_2BYTE_INDEX_EN   (1<<31)
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c 
> b/drivers/gpu/drm/i915/intel_i2c.c
> index a64f26c..1369fc4 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -114,8 +114,8 @@ intel_i2c_reset(struct drm_device *dev)
>  {
>   struct drm_i915_private *dev_priv = dev->dev_private;
>  
> - I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
> - I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
> + I915_WRITE(GMBUS0, 0);
> + I915_WRITE(GMBUS4, 0);
>  }
>  
>  static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool 
> enable)
> @@ -261,7 +261,6 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
>u32 gmbus4_irq_en)
>  {
>   int i;
> - int reg_offset = dev_priv->gpio_mmio_base;
>   u32 gmbus2 = 0;
>   DEFINE_WAIT(wait);
>  
> @@ -271,13 +270,13 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
>   /* Important: The hw handles only the first bit, so set only one! Since
>* we also need to check for NAKs besides the hw ready/idle signal, we
>* need to wake up periodically and check that ourselves. */
> - I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
> + I915_WRITE(GMBUS4, gmbus4_irq_en);
>  
>   for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
>   prepare_to_wait(_priv->gmbus_wait_queue, ,
>   TASK_UNINTERRUPTIBLE);
>  
> - gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
> + gmbus2 = I915_READ_NOTRACE(GMBUS2);
>   if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
>   break;
>  
> @@ -285,7 +284,7 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
>   }
>   finish_wait(_priv->gmbus_wait_queue, );
>  
> - I915_WRITE(GMBUS4 + reg_offset, 0);
> + I915_WRITE(GMBUS4, 0);
>  
>   if (gmbus2 & GMBUS_SATOER)
>   return -ENXIO;
> @@ -298,20 +297,19 @@ static int
>

[Intel-gfx] [PATCH 25/43] drm/i915: Include gpio_mmio_base in GMBUS reg defines

2015-09-18 Thread ville . syrjala

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  | 12 -
 drivers/gpu/drm/i915/intel_i2c.c | 54 +---
 2 files changed, 29 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b35e24f..0216771 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2114,7 +2114,7 @@ enum skl_disp_power_wells {
 # define GPIO_DATA_VAL_IN  (1 << 12)
 # define GPIO_DATA_PULLUP_DISABLE  (1 << 13)
 
-#define GMBUS0 0x5100 /* clock/port select */
+#define GMBUS0 (dev_priv->gpio_mmio_base + 0x5100) /* 
clock/port select */
 #define   GMBUS_RATE_100KHZ(0<<8)
 #define   GMBUS_RATE_50KHZ (1<<8)
 #define   GMBUS_RATE_400KHZ(2<<8) /* reserved on Pineview */
@@ -2133,7 +2133,7 @@ enum skl_disp_power_wells {
 #define   GMBUS_PIN_2_BXT  2
 #define   GMBUS_PIN_3_BXT  3
 #define   GMBUS_NUM_PINS   7 /* including 0 */
-#define GMBUS1 0x5104 /* command/status */
+#define GMBUS1 (dev_priv->gpio_mmio_base + 0x5104) /* 
command/status */
 #define   GMBUS_SW_CLR_INT (1<<31)
 #define   GMBUS_SW_RDY (1<<30)
 #define   GMBUS_ENT(1<<29) /* enable timeout */
@@ -2147,7 +2147,7 @@ enum skl_disp_power_wells {
 #define   GMBUS_SLAVE_ADDR_SHIFT 1
 #define   GMBUS_SLAVE_READ (1<<0)
 #define   GMBUS_SLAVE_WRITE(0<<0)
-#define GMBUS2 0x5108 /* status */
+#define GMBUS2 (dev_priv->gpio_mmio_base + 0x5108) /* status */
 #define   GMBUS_INUSE  (1<<15)
 #define   GMBUS_HW_WAIT_PHASE  (1<<14)
 #define   GMBUS_STALL_TIMEOUT  (1<<13)
@@ -2155,14 +2155,14 @@ enum skl_disp_power_wells {
 #define   GMBUS_HW_RDY (1<<11)
 #define   GMBUS_SATOER (1<<10)
 #define   GMBUS_ACTIVE (1<<9)
-#define GMBUS3 0x510c /* data buffer bytes 3-0 */
-#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
+#define GMBUS3 (dev_priv->gpio_mmio_base + 0x510c) /* data 
buffer bytes 3-0 */
+#define GMBUS4 (dev_priv->gpio_mmio_base + 0x5110) /* 
interrupt mask (Pineview+) */
 #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
 #define   GMBUS_NAK_EN (1<<3)
 #define   GMBUS_IDLE_EN(1<<2)
 #define   GMBUS_HW_WAIT_EN (1<<1)
 #define   GMBUS_HW_RDY_EN  (1<<0)
-#define GMBUS5 0x5120 /* byte index */
+#define GMBUS5 (dev_priv->gpio_mmio_base + 0x5120) /* byte 
index */
 #define   GMBUS_2BYTE_INDEX_EN (1<<31)
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index a64f26c..1369fc4 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -114,8 +114,8 @@ intel_i2c_reset(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
-   I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
+   I915_WRITE(GMBUS0, 0);
+   I915_WRITE(GMBUS4, 0);
 }
 
 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
@@ -261,7 +261,6 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 u32 gmbus4_irq_en)
 {
int i;
-   int reg_offset = dev_priv->gpio_mmio_base;
u32 gmbus2 = 0;
DEFINE_WAIT(wait);
 
@@ -271,13 +270,13 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
/* Important: The hw handles only the first bit, so set only one! Since
 * we also need to check for NAKs besides the hw ready/idle signal, we
 * need to wake up periodically and check that ourselves. */
-   I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
+   I915_WRITE(GMBUS4, gmbus4_irq_en);
 
for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
prepare_to_wait(_priv->gmbus_wait_queue, ,
TASK_UNINTERRUPTIBLE);
 
-   gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
+   gmbus2 = I915_READ_NOTRACE(GMBUS2);
if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
break;
 
@@ -285,7 +284,7 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
}
finish_wait(_priv->gmbus_wait_queue, );
 
-   I915_WRITE(GMBUS4 + reg_offset, 0);
+   I915_WRITE(GMBUS4, 0);
 
if (gmbus2 & GMBUS_SATOER)
return -ENXIO;
@@ -298,20 +297,19 @@ static int
 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 {
int ret;
-   int reg_offset = dev_priv->gpio_mmio_base;
 
-#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
+#define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0)
 
if (!HAS_GMBUS_IRQ(dev_priv->dev))
return wait_for(C, 10);

Re: [Intel-gfx] [PATCH 25/43] drm/i915: Include gpio_mmio_base in GMBUS reg defines

[Intel-gfx] [PATCH 25/43] drm/i915: Include gpio_mmio_base in GMBUS reg defines

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