Re: [Intel-gfx] [PATCH 26/27] drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register

[Rodrigo Vivi]

On Tue, Jan 09, 2018 at 11:28:34PM +, Paulo Zanoni wrote:
> This enables the Mesa driver to advertise support for ARB_timer_query,
> and thus an OpenGL version higher than 3.2.
> 
> Based on the CNL patch by Nanley Chery.
> 
> v2: Rebase.
> 
> Cc: Anuj Phogat 
> Cc: Nanley Chery 
> Cc: Rodrigo Vivi 
> Requested-by: Anuj Phogat 
> Tested-by: Anuj Phogat 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> b/drivers/gpu/drm/i915/intel_uncore.c
> index c49beb326414..ae1196b6e1f4 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1588,7 +1588,7 @@ static const struct reg_whitelist {
>  } reg_read_whitelist[] = { {
>   .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
>   .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
> - .gen_mask = INTEL_GEN_MASK(4, 10),
> + .gen_mask = INTEL_GEN_MASK(4, 11),

I don't like this mask, but I don't have better solutions and
I'm glad we didn't forget to this gen.


Reviewed-by: Rodrigo Vivi 



>   .size = 8
>  } };
>  
> -- 
> 2.14.3
> 
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[Intel-gfx] [PATCH 26/27] drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register

[Paulo Zanoni]

This enables the Mesa driver to advertise support for ARB_timer_query,
and thus an OpenGL version higher than 3.2.

Based on the CNL patch by Nanley Chery.

v2: Rebase.

Cc: Anuj Phogat 
Cc: Nanley Chery 
Cc: Rodrigo Vivi 
Requested-by: Anuj Phogat 
Tested-by: Anuj Phogat 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_uncore.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index c49beb326414..ae1196b6e1f4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1588,7 +1588,7 @@ static const struct reg_whitelist {
 } reg_read_whitelist[] = { {
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
-   .gen_mask = INTEL_GEN_MASK(4, 10),
+   .gen_mask = INTEL_GEN_MASK(4, 11),
.size = 8
 } };
 
-- 
2.14.3

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