Re: [Intel-gfx] [PATCH 27/67] drm/i915/cnl: Also need power well sanitize.

2017-06-05 Thread Imre Deak 
On Thu, Apr 06, 2017 at 12:15:23PM -0700, Rodrigo Vivi wrote:
> The workaround added in
> commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
> equests left on by DMC/KVMR")
> needs to be applied on Cannonlake as well.
> 
> So let's assume any platform using this power well setup
> will also need and let's just go ahead and remove if condition.
> 
> Cc: Imre Deak 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Imre Deak 

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index c67eb89..1797c91 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -855,8 +855,7 @@ static void skl_set_power_well(struct drm_i915_private 
> *dev_priv,
>   DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
>   }
>  
> - if (IS_GEN9(dev_priv))
> - gen9_sanitize_power_well_requests(dev_priv, power_well);
> + gen9_sanitize_power_well_requests(dev_priv, power_well);
>   }
>  
>   if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH 27/67] drm/i915/cnl: Also need power well sanitize.

2017-04-13 Thread Vivi, Rodrigo 
On Thu, 2017-04-13 at 17:44 +0300, Imre Deak wrote:
> On Thu, Apr 06, 2017 at 12:15:23PM -0700, Rodrigo Vivi wrote:
> > The workaround added in
> > commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
> > equests left on by DMC/KVMR")
> > needs to be applied on Cannonlake as well.
> > 
> > So let's assume any platform using this power well setup
> > will also need and let's just go ahead and remove if condition.
> > 
> > Cc: Imre Deak 
> > Signed-off-by: Rodrigo Vivi 
> 
> Do you know if this is really needed on CNL, that is the
> HSW_PWR_WELL_DEBUG reg has request bits that the WA clears? If so,
> I'd feel easier if we could get BSpec updated with the expected
> programming for this.

Yes, we do need. Without this some power well times out.

> 
> --Imre
> 
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index c67eb89..1797c91 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -855,8 +855,7 @@ static void skl_set_power_well(struct drm_i915_private 
> > *dev_priv,
> > DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> > }
> >  
> > -   if (IS_GEN9(dev_priv))
> > -   gen9_sanitize_power_well_requests(dev_priv, power_well);
> > +   gen9_sanitize_power_well_requests(dev_priv, power_well);
> > }
> >  
> > if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> > -- 
> > 1.9.1
> > 

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Re: [Intel-gfx] [PATCH 27/67] drm/i915/cnl: Also need power well sanitize.

2017-04-13 Thread Imre Deak 
On Thu, Apr 06, 2017 at 12:15:23PM -0700, Rodrigo Vivi wrote:
> The workaround added in
> commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
> equests left on by DMC/KVMR")
> needs to be applied on Cannonlake as well.
> 
> So let's assume any platform using this power well setup
> will also need and let's just go ahead and remove if condition.
> 
> Cc: Imre Deak 
> Signed-off-by: Rodrigo Vivi 

Do you know if this is really needed on CNL, that is the
HSW_PWR_WELL_DEBUG reg has request bits that the WA clears? If so,
I'd feel easier if we could get BSpec updated with the expected
programming for this.

--Imre

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index c67eb89..1797c91 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -855,8 +855,7 @@ static void skl_set_power_well(struct drm_i915_private 
> *dev_priv,
>   DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
>   }
>  
> - if (IS_GEN9(dev_priv))
> - gen9_sanitize_power_well_requests(dev_priv, power_well);
> + gen9_sanitize_power_well_requests(dev_priv, power_well);
>   }
>  
>   if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> -- 
> 1.9.1
> 
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[Intel-gfx] [PATCH 27/67] drm/i915/cnl: Also need power well sanitize.

2017-04-06 Thread Rodrigo Vivi 
The workaround added in
commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
equests left on by DMC/KVMR")
needs to be applied on Cannonlake as well.

So let's assume any platform using this power well setup
will also need and let's just go ahead and remove if condition.

Cc: Imre Deak 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index c67eb89..1797c91 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -855,8 +855,7 @@ static void skl_set_power_well(struct drm_i915_private 
*dev_priv,
DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
}
 
-   if (IS_GEN9(dev_priv))
-   gen9_sanitize_power_well_requests(dev_priv, power_well);
+   gen9_sanitize_power_well_requests(dev_priv, power_well);
}
 
if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
-- 
1.9.1

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