subject:"\[Intel\-gfx\] \[PATCH 3\/3\] drm\/i915\/mtl\: C6 residency and C state type for MTL SAMedia"

Re: [Intel-gfx] [PATCH 3/3] drm/i915/mtl: C6 residency and C state type for MTL SAMedia

2022-10-19 Thread Dixit, Ashutosh

On Mon, 17 Oct 2022 13:12:33 -0700, Dixit, Ashutosh wrote:
>
> On Fri, 14 Oct 2022 20:26:18 -0700, Ashutosh Dixit wrote:
> >
> > From: Badal Nilawar 
>
> Hi Badal,
>
> One question below.
>
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
> > b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > index 1fb053cbf52db..3a9bb4387248e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > @@ -256,6 +256,61 @@ static int ilk_drpc(struct seq_file *m)
> > return 0;
> >  }
> >
> > +static int mtl_drpc(struct seq_file *m)
> > +{
>
> Here we have:
>
> > +   global_forcewake = intel_uncore_read(uncore, FORCEWAKE_GT_GEN9);
> and
> > +   seq_printf(m, "Global Forcewake Requests: 0x%x\n", global_forcewake);
>
> In gen6_drpc we have:
>
>   mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
> and
>   seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
>
> Also:
>   #define FORCEWAKE_MT_MMIO(0xa188)
>   #define FORCEWAKE_GT_GEN9   _MMIO(0xa188)
>
> So they are both the same register. So what is the reason for this
> difference, which one should we use?
>
> Also let's have the prints in the same order as gen6_drpc (move fw request
> before rc6 residency).

This has been made identical to gen6_drpc in series v8.

Thanks.
--
Ashutosh

Re: [Intel-gfx] [PATCH 3/3] drm/i915/mtl: C6 residency and C state type for MTL SAMedia

2022-10-17 Thread Dixit, Ashutosh

On Fri, 14 Oct 2022 20:26:18 -0700, Ashutosh Dixit wrote:
>
> From: Badal Nilawar 

Hi Badal,

One question below.

> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
> b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 1fb053cbf52db..3a9bb4387248e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -256,6 +256,61 @@ static int ilk_drpc(struct seq_file *m)
>   return 0;
>  }
>
> +static int mtl_drpc(struct seq_file *m)
> +{

Here we have:

> + global_forcewake = intel_uncore_read(uncore, FORCEWAKE_GT_GEN9);
and
> + seq_printf(m, "Global Forcewake Requests: 0x%x\n", global_forcewake);

In gen6_drpc we have:

mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
and
seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);

Also:
#define FORCEWAKE_MT_MMIO(0xa188)
#define FORCEWAKE_GT_GEN9   _MMIO(0xa188)

So they are both the same register. So what is the reason for this
difference, which one should we use?

Also let's have the prints in the same order as gen6_drpc (move fw request
before rc6 residency).

Thanks.
--
Ashutosh

[Intel-gfx] [PATCH 3/3] drm/i915/mtl: C6 residency and C state type for MTL SAMedia

2022-10-14 Thread Ashutosh Dixit

From: Badal Nilawar 

Add support for C6 residency and C state type for MTL SAMedia. Also add
mtl_drpc.

v2: Fixed review comments (Ashutosh)
v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
Remove MTL_CC_SHIFT (Ashutosh)
Adapt to RC6 residency register code refactor (Jani N)

Signed-off-by: Ashutosh Dixit 
Signed-off-by: Badal Nilawar 
---
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 57 +++
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  5 ++
 drivers/gpu/drm/i915/gt/intel_rc6.c   | 17 --
 3 files changed, 75 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 1fb053cbf52db..3a9bb4387248e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -256,6 +256,61 @@ static int ilk_drpc(struct seq_file *m)
return 0;
 }
 
+static int mtl_drpc(struct seq_file *m)
+{
+   struct intel_gt *gt = m->private;
+   struct intel_uncore *uncore = gt->uncore;
+   u32 gt_core_status, rcctl1, global_forcewake;
+   u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
+
+   gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+
+   global_forcewake = intel_uncore_read(uncore, FORCEWAKE_GT_GEN9);
+
+   rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
+   mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
+   mtl_powergate_status = intel_uncore_read(uncore,
+GEN9_PWRGT_DOMAIN_STATUS);
+
+   seq_printf(m, "RC6 Enabled: %s\n",
+  str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+   if (gt->type == GT_MEDIA) {
+   seq_printf(m, "Media Well Gating Enabled: %s\n",
+  str_yes_no(mtl_powergate_enable & 
GEN9_MEDIA_PG_ENABLE));
+   } else {
+   seq_printf(m, "Render Well Gating Enabled: %s\n",
+  str_yes_no(mtl_powergate_enable & 
GEN9_RENDER_PG_ENABLE));
+   }
+
+   seq_puts(m, "Current RC state: ");
+   switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) {
+   case MTL_CC0:
+   seq_puts(m, "on\n");
+   break;
+   case MTL_CC6:
+   seq_puts(m, "RC6\n");
+   break;
+   default:
+   seq_puts(m, "Unknown\n");
+   break;
+   }
+
+   if (gt->type == GT_MEDIA)
+   seq_printf(m, "Media Power Well: %s\n",
+  (mtl_powergate_status &
+   GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+   else
+   seq_printf(m, "Render Power Well: %s\n",
+  (mtl_powergate_status &
+   GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+
+   intel_rc6_print_rc6_res(m, "RC6 residency since boot:", 
RC6_RES_REG_RC6);
+
+   seq_printf(m, "Global Forcewake Requests: 0x%x\n", global_forcewake);
+
+   return fw_domains_show(m, NULL);
+}
+
 static int drpc_show(struct seq_file *m, void *unused)
 {
struct intel_gt *gt = m->private;
@@ -266,6 +321,8 @@ static int drpc_show(struct seq_file *m, void *unused)
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_drpc(m);
+   else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+   err = mtl_drpc(m);
else if (GRAPHICS_VER(i915) >= 6)
err = gen6_drpc(m);
else
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 66867747f643e..0493ea324b846 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -11,6 +11,9 @@
 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
 #define MTL_MIRROR_TARGET_WP1  _MMIO(0xc60)
 #define   MTL_CAGF_MASKREG_GENMASK(8, 0)
+#define   MTL_CC0  0x0
+#define   MTL_CC6  0x3
+#define   MTL_CC_MASK  REG_GENMASK(12, 9)
 
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0_MMIO(0xd00)
@@ -1494,6 +1497,8 @@
 #define FORCEWAKE_MEDIA_VLV_MMIO(0x1300b8)
 #define FORCEWAKE_ACK_MEDIA_VLV_MMIO(0x1300bc)
 
+#define MTL_MEDIA_MC6  _MMIO(0x138048)
+
 #define GEN6_GT_THREAD_STATUS_REG  _MMIO(0x13805c)
 #define   GEN6_GT_THREAD_STATUS_CORE_MASK  0x7
 
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 794f77fa10c55..1a1b2289c706c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -553,10 +553,19 @@ static void

Re: [Intel-gfx] [PATCH 3/3] drm/i915/mtl: C6 residency and C state type for MTL SAMedia

Re: [Intel-gfx] [PATCH 3/3] drm/i915/mtl: C6 residency and C state type for MTL SAMedia

[Intel-gfx] [PATCH 3/3] drm/i915/mtl: C6 residency and C state type for MTL SAMedia

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