Re: [Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

2018-11-30 Thread Daniel Vetter 
On Thu, Nov 29, 2018 at 05:52:28PM +, Strasser, Kevin wrote:
> Daniel Vetter wrote:
> > Do we have end-to-end userspace for this?
> 
> I have patches for IGT and I'm planning on adding usage code to Weston. Apart
> from that there is a Windows use case that Tina mentioned previously. I take
> it that you will need to see the Weston part before accepting this.

Yup.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

2018-11-29 Thread Strasser, Kevin 
Ville Syrjälä wrote:
> On Wed, Nov 28, 2018 at 10:38:13PM -0800, Kevin Strasser wrote:
>> 64 bpp half float formats are supported on hdr planes only and are subject
>> to the following restrictions:
>>   * 90/270 rotation not supported
>>   * Yf Tiling not supported
>>   * Frame Buffer Compression not supported
>>   * Color Keying not supported
>
> Is scaling supported? It wasn't on earlier platforms.

Yes, ICL does support scaling for these formats.

Thanks,
Kevin
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

2018-11-29 Thread Ville Syrjälä 
On Wed, Nov 28, 2018 at 10:38:13PM -0800, Kevin Strasser wrote:
> 64 bpp half float formats are supported on hdr planes only and are subject
> to the following restrictions:
>   * 90/270 rotation not supported
>   * Yf Tiling not supported
>   * Frame Buffer Compression not supported
>   * Color Keying not supported

Is scaling supported? It wasn't on earlier platforms.

> 
> The behavior of pixel normalize with non-float formats is currently
> undefined. As such, the pixel normalize register is enabled iff the
> framebuffer contains floating point pixel data.
> 
> Signed-off-by: Kevin Strasser 
> Cc: Uma Shankar 
> Cc: Shashank Sharma 
> Cc: Ville Syrjälä 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: dri-de...@lists.freedesktop.org
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 15 ++-
>  drivers/gpu/drm/i915/intel_display.c | 48 +
>  drivers/gpu/drm/i915/intel_drv.h |  5 +++
>  drivers/gpu/drm/i915/intel_sprite.c  | 82 
> +---
>  4 files changed, 143 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 47baf2fe..871d293 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6563,6 +6563,10 @@ enum {
>  #define _PLANE_KEYMAX_1_A0x701a0
>  #define _PLANE_KEYMAX_2_A0x702a0
>  #define  PLANE_KEYMAX_ALPHA(a)   ((a) << 24)
> +#define _PLANE_PIXEL_NORMALIZE_1_A   0x701a8
> +#define _PLANE_PIXEL_NORMALIZE_2_A   0x702a8
> +#define   PLANE_PIXEL_NORMALIZE_ENABLE   (1 << 31)
> +#define   PLANE_PIXEL_NORMALIZE_FACTOR_MASK  0x
>  #define _PLANE_AUX_DIST_1_A  0x701c0
>  #define _PLANE_AUX_DIST_2_A  0x702c0
>  #define _PLANE_AUX_OFFSET_1_A0x701c4
> @@ -6786,7 +6790,16 @@ enum {
>  #define PLANE_COLOR_CTL(pipe, plane) \
>   _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
>  
> -#/* SKL new cursor registers */
> +#define _PLANE_PIXEL_NORMALIZE_1_B   0x711a8
> +#define _PLANE_PIXEL_NORMALIZE_2_B   0x712a8
> +#define _PLANE_PIXEL_NORMALIZE_1(pipe) \
> + _PIPE(pipe, _PLANE_PIXEL_NORMALIZE_1_A, _PLANE_PIXEL_NORMALIZE_1_B)
> +#define _PLANE_PIXEL_NORMALIZE_2(pipe) \
> + _PIPE(pipe, _PLANE_PIXEL_NORMALIZE_2_A, _PLANE_PIXEL_NORMALIZE_2_B)
> +#define PLANE_PIXEL_NORMALIZE(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_PIXEL_NORMALIZE_1(pipe), 
> _PLANE_PIXEL_NORMALIZE_2(pipe))
> +
> +/* SKL new cursor registers */
>  #define _CUR_BUF_CFG_A   0x7017c
>  #define _CUR_BUF_CFG_B   0x7117c
>  #define CUR_BUF_CFG(pipe)_MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index e9f4e22..cbacb4b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2618,6 +2618,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, 
> bool alpha)
>   return DRM_FORMAT_RGB565;
>   case PLANE_CTL_FORMAT_NV12:
>   return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_XRGB_16161616F:
> + if (rgb_order) {
> + if (alpha)
> + return DRM_FORMAT_ABGR16161616H;
> + else
> + return DRM_FORMAT_XBGR16161616H;
> + } else {
> + if (alpha)
> + return DRM_FORMAT_ARGB16161616H;
> + else
> + return DRM_FORMAT_XRGB16161616H;
> + }
>   default:
>   case PLANE_CTL_FORMAT_XRGB_:
>   if (rgb_order) {
> @@ -3505,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>   case DRM_FORMAT_NV12:
>   return PLANE_CTL_FORMAT_NV12;
> + case DRM_FORMAT_XBGR16161616H:
> + case DRM_FORMAT_ABGR16161616H:
> + return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
> + case DRM_FORMAT_XRGB16161616H:
> + case DRM_FORMAT_ARGB16161616H:
> + return PLANE_CTL_FORMAT_XRGB_16161616F;
>   default:
>   MISSING_CASE(pixel_format);
>   }
> @@ -3680,6 +3698,32 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
> *crtc_state,
>   return plane_color_ctl;
>  }
>  
> +u32 icl_plane_pixel_normalize(uint32_t pixel_format,
> +   enum drm_pixel_normalize_range range)
> +{
> + /* 1.0 in half float */
> + u16 half_float_1 = 0x3c00;
> + /* 3.92E-3 in half float */
> + u16 half_float_255 = 0x1c04;
> +
> + switch (pixel_format) {
> + case DRM_FORMAT_XRGB16161616H:
> + case DRM_FORMAT_XBGR16161616H:
> + case DRM_FORMAT_ARGB16161616H:
> + case DRM_FORMAT_ABGR1

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

2018-11-29 Thread Strasser, Kevin 
Daniel Vetter wrote:
> Do we have end-to-end userspace for this?

I have patches for IGT and I'm planning on adding usage code to Weston. Apart
from that there is a Windows use case that Tina mentioned previously. I take
it that you will need to see the Weston part before accepting this.

Thanks,
Kevin
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

2018-11-29 Thread Daniel Vetter 
On Wed, Nov 28, 2018 at 10:38:13PM -0800, Kevin Strasser wrote:
> 64 bpp half float formats are supported on hdr planes only and are subject
> to the following restrictions:
>   * 90/270 rotation not supported
>   * Yf Tiling not supported
>   * Frame Buffer Compression not supported
>   * Color Keying not supported
> 
> The behavior of pixel normalize with non-float formats is currently
> undefined. As such, the pixel normalize register is enabled iff the
> framebuffer contains floating point pixel data.
> 
> Signed-off-by: Kevin Strasser 
> Cc: Uma Shankar 
> Cc: Shashank Sharma 
> Cc: Ville Syrjälä 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: dri-de...@lists.freedesktop.org

Do we have end-to-end userspace for this?
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 15 ++-
>  drivers/gpu/drm/i915/intel_display.c | 48 +
>  drivers/gpu/drm/i915/intel_drv.h |  5 +++
>  drivers/gpu/drm/i915/intel_sprite.c  | 82 
> +---
>  4 files changed, 143 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 47baf2fe..871d293 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6563,6 +6563,10 @@ enum {
>  #define _PLANE_KEYMAX_1_A0x701a0
>  #define _PLANE_KEYMAX_2_A0x702a0
>  #define  PLANE_KEYMAX_ALPHA(a)   ((a) << 24)
> +#define _PLANE_PIXEL_NORMALIZE_1_A   0x701a8
> +#define _PLANE_PIXEL_NORMALIZE_2_A   0x702a8
> +#define   PLANE_PIXEL_NORMALIZE_ENABLE   (1 << 31)
> +#define   PLANE_PIXEL_NORMALIZE_FACTOR_MASK  0x
>  #define _PLANE_AUX_DIST_1_A  0x701c0
>  #define _PLANE_AUX_DIST_2_A  0x702c0
>  #define _PLANE_AUX_OFFSET_1_A0x701c4
> @@ -6786,7 +6790,16 @@ enum {
>  #define PLANE_COLOR_CTL(pipe, plane) \
>   _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
>  
> -#/* SKL new cursor registers */
> +#define _PLANE_PIXEL_NORMALIZE_1_B   0x711a8
> +#define _PLANE_PIXEL_NORMALIZE_2_B   0x712a8
> +#define _PLANE_PIXEL_NORMALIZE_1(pipe) \
> + _PIPE(pipe, _PLANE_PIXEL_NORMALIZE_1_A, _PLANE_PIXEL_NORMALIZE_1_B)
> +#define _PLANE_PIXEL_NORMALIZE_2(pipe) \
> + _PIPE(pipe, _PLANE_PIXEL_NORMALIZE_2_A, _PLANE_PIXEL_NORMALIZE_2_B)
> +#define PLANE_PIXEL_NORMALIZE(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_PIXEL_NORMALIZE_1(pipe), 
> _PLANE_PIXEL_NORMALIZE_2(pipe))
> +
> +/* SKL new cursor registers */
>  #define _CUR_BUF_CFG_A   0x7017c
>  #define _CUR_BUF_CFG_B   0x7117c
>  #define CUR_BUF_CFG(pipe)_MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index e9f4e22..cbacb4b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2618,6 +2618,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, 
> bool alpha)
>   return DRM_FORMAT_RGB565;
>   case PLANE_CTL_FORMAT_NV12:
>   return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_XRGB_16161616F:
> + if (rgb_order) {
> + if (alpha)
> + return DRM_FORMAT_ABGR16161616H;
> + else
> + return DRM_FORMAT_XBGR16161616H;
> + } else {
> + if (alpha)
> + return DRM_FORMAT_ARGB16161616H;
> + else
> + return DRM_FORMAT_XRGB16161616H;
> + }
>   default:
>   case PLANE_CTL_FORMAT_XRGB_:
>   if (rgb_order) {
> @@ -3505,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>   case DRM_FORMAT_NV12:
>   return PLANE_CTL_FORMAT_NV12;
> + case DRM_FORMAT_XBGR16161616H:
> + case DRM_FORMAT_ABGR16161616H:
> + return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
> + case DRM_FORMAT_XRGB16161616H:
> + case DRM_FORMAT_ARGB16161616H:
> + return PLANE_CTL_FORMAT_XRGB_16161616F;
>   default:
>   MISSING_CASE(pixel_format);
>   }
> @@ -3680,6 +3698,32 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
> *crtc_state,
>   return plane_color_ctl;
>  }
>  
> +u32 icl_plane_pixel_normalize(uint32_t pixel_format,
> +   enum drm_pixel_normalize_range range)
> +{
> + /* 1.0 in half float */
> + u16 half_float_1 = 0x3c00;
> + /* 3.92E-3 in half float */
> + u16 half_float_255 = 0x1c04;
> +
> + switch (pixel_format) {
> + case DRM_FORMAT_XRGB16161616H:
> + case DRM_FORMAT_XBGR16161616H:
> + case DRM_FORMAT_ARGB16161616H:
> + case DRM_FORMAT_ABGR16161

[Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

2018-11-28 Thread Kevin Strasser 
64 bpp half float formats are supported on hdr planes only and are subject
to the following restrictions:
  * 90/270 rotation not supported
  * Yf Tiling not supported
  * Frame Buffer Compression not supported
  * Color Keying not supported

The behavior of pixel normalize with non-float formats is currently
undefined. As such, the pixel normalize register is enabled iff the
framebuffer contains floating point pixel data.

Signed-off-by: Kevin Strasser 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Cc: Ville Syrjälä 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/i915/i915_reg.h  | 15 ++-
 drivers/gpu/drm/i915/intel_display.c | 48 +
 drivers/gpu/drm/i915/intel_drv.h |  5 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 82 +---
 4 files changed, 143 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47baf2fe..871d293 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6563,6 +6563,10 @@ enum {
 #define _PLANE_KEYMAX_1_A  0x701a0
 #define _PLANE_KEYMAX_2_A  0x702a0
 #define  PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_PIXEL_NORMALIZE_1_A 0x701a8
+#define _PLANE_PIXEL_NORMALIZE_2_A 0x702a8
+#define   PLANE_PIXEL_NORMALIZE_ENABLE (1 << 31)
+#define   PLANE_PIXEL_NORMALIZE_FACTOR_MASK0x
 #define _PLANE_AUX_DIST_1_A0x701c0
 #define _PLANE_AUX_DIST_2_A0x702c0
 #define _PLANE_AUX_OFFSET_1_A  0x701c4
@@ -6786,7 +6790,16 @@ enum {
 #define PLANE_COLOR_CTL(pipe, plane)   \
_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
 
-#/* SKL new cursor registers */
+#define _PLANE_PIXEL_NORMALIZE_1_B 0x711a8
+#define _PLANE_PIXEL_NORMALIZE_2_B 0x712a8
+#define _PLANE_PIXEL_NORMALIZE_1(pipe) \
+   _PIPE(pipe, _PLANE_PIXEL_NORMALIZE_1_A, _PLANE_PIXEL_NORMALIZE_1_B)
+#define _PLANE_PIXEL_NORMALIZE_2(pipe) \
+   _PIPE(pipe, _PLANE_PIXEL_NORMALIZE_2_A, _PLANE_PIXEL_NORMALIZE_2_B)
+#define PLANE_PIXEL_NORMALIZE(pipe, plane) \
+   _MMIO_PLANE(plane, _PLANE_PIXEL_NORMALIZE_1(pipe), 
_PLANE_PIXEL_NORMALIZE_2(pipe))
+
+/* SKL new cursor registers */
 #define _CUR_BUF_CFG_A 0x7017c
 #define _CUR_BUF_CFG_B 0x7117c
 #define CUR_BUF_CFG(pipe)  _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e9f4e22..cbacb4b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2618,6 +2618,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, 
bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+   case PLANE_CTL_FORMAT_XRGB_16161616F:
+   if (rgb_order) {
+   if (alpha)
+   return DRM_FORMAT_ABGR16161616H;
+   else
+   return DRM_FORMAT_XBGR16161616H;
+   } else {
+   if (alpha)
+   return DRM_FORMAT_ARGB16161616H;
+   else
+   return DRM_FORMAT_XRGB16161616H;
+   }
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3505,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+   case DRM_FORMAT_XBGR16161616H:
+   case DRM_FORMAT_ABGR16161616H:
+   return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
+   case DRM_FORMAT_XRGB16161616H:
+   case DRM_FORMAT_ARGB16161616H:
+   return PLANE_CTL_FORMAT_XRGB_16161616F;
default:
MISSING_CASE(pixel_format);
}
@@ -3680,6 +3698,32 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
*crtc_state,
return plane_color_ctl;
 }
 
+u32 icl_plane_pixel_normalize(uint32_t pixel_format,
+ enum drm_pixel_normalize_range range)
+{
+   /* 1.0 in half float */
+   u16 half_float_1 = 0x3c00;
+   /* 3.92E-3 in half float */
+   u16 half_float_255 = 0x1c04;
+
+   switch (pixel_format) {
+   case DRM_FORMAT_XRGB16161616H:
+   case DRM_FORMAT_XBGR16161616H:
+   case DRM_FORMAT_ARGB16161616H:
+   case DRM_FORMAT_ABGR16161616H:
+   switch (range) {
+   case DRM_PIXEL_NORMALIZE_RANGE_0_1:
+   return PLANE_PIXEL_NORMALIZE_ENABLE | half_float_1;
+   case DRM_PIXEL_NORMALIZE_RANGE_0_255:
+   return PLANE_PIXEL_NOR