[Intel-gfx] [PATCH 3/3] drm/i915: Splitting PPS functions based on platform
Modifying PPS functions in intel_dp.c to avoid using too many conditional
statements based on platform.
Calling vlv_initial_power_sequencer_setup() from vlv specific pps functions
to just initialize vlv specific data and continue with the rest of the generic
code.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 215 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 +
2 files changed, 146 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1d4bf78..1c6b4b3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -520,8 +520,6 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
DRM_DEBUG_KMS(initial power sequencer for port %c: pipe %c\n,
port_name(port), pipe_name(intel_dp-pps_pipe));
- intel_dp_init_panel_power_sequencer(dev, intel_dp);
- intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
}
void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
@@ -4714,6 +4712,7 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp)
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
+ struct drm_device *dev = encoder-dev;
struct intel_dp *intel_dp;
if (to_intel_encoder(encoder)-type != INTEL_OUTPUT_EDP)
@@ -4727,8 +4726,10 @@ static void intel_dp_encoder_reset(struct drm_encoder
*encoder)
* Read out the current power sequencer assignment,
* in case the BIOS did something with it.
*/
- if (IS_VALLEYVIEW(encoder-dev))
- vlv_initial_power_sequencer_setup(intel_dp);
+ if (IS_VALLEYVIEW(dev)) {
+ intel_dp_init_panel_power_sequencer(dev, intel_dp);
+ intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
+ }
intel_edp_panel_vdd_sanitize(intel_dp);
@@ -4917,45 +4918,26 @@ static void intel_dp_init_panel_power_timestamps(struct
intel_dp *intel_dp)
intel_dp-last_backlight_off = jiffies;
}
-static void
-intel_dp_init_panel_power_sequencer(struct drm_device *dev,
- struct intel_dp *intel_dp)
+static struct edp_power_seq pch_get_pps_registers(
+ struct intel_dp *intel_dp,
+ u32 pp_ctrl_reg, u32 pp_on_reg,
+ u32 pp_off_reg, u32 pp_div_reg)
{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port-base.base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
- struct edp_power_seq cur, vbt, spec,
- *final = intel_dp-pps_delays;
u32 pp_on, pp_off, pp_div, pp;
- int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
-
- lockdep_assert_held(dev_priv-pps_mutex);
+ struct edp_power_seq cur;
- /* already initialized? */
- if (final-t11_t12 != 0)
- return;
-
- if (HAS_PCH_SPLIT(dev)) {
- pp_ctrl_reg = PCH_PP_CONTROL;
- pp_on_reg = PCH_PP_ON_DELAYS;
- pp_off_reg = PCH_PP_OFF_DELAYS;
- pp_div_reg = PCH_PP_DIVISOR;
- } else {
- enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
-
- pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
- pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
- pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
- pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
- }
+ pp_on = I915_READ(pp_on_reg);
+ pp_off = I915_READ(pp_off_reg);
+ pp_div = I915_READ(pp_div_reg);
/* Workaround: Need to write PP_CONTROL with the unlock key as
* the very first thing. */
pp = ironlake_get_pp_control(intel_dp);
I915_WRITE(pp_ctrl_reg, pp);
- pp_on = I915_READ(pp_on_reg);
- pp_off = I915_READ(pp_off_reg);
- pp_div = I915_READ(pp_div_reg);
-
/* Pull timing values out of registers */
cur.t1_t3 = (pp_on PANEL_POWER_UP_DELAY_MASK)
PANEL_POWER_UP_DELAY_SHIFT;
@@ -4970,10 +4952,61 @@ intel_dp_init_panel_power_sequencer(struct drm_device
*dev,
PANEL_POWER_DOWN_DELAY_SHIFT;
cur.t11_t12 = ((pp_div PANEL_POWER_CYCLE_DELAY_MASK)
- PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
+ PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
DRM_DEBUG_KMS(cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n,
- cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
+ cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
+
+ return cur;
+}
+
+
+static struct edp_power_seq pch_setup_pps(struct intel_dp *intel_dp)
+{
+ int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
+
+ pp_ctrl_reg = PCH_PP_CONTROL;
+ pp_on_reg = PCH_PP_ON_DELAYS;
+
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Splitting PPS functions based on
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform: baseline_drm_intel_nightly_pass_rate-patch_applied_pass_rate BYT: pass/total=277/348-276/348 PNV: pass/total=323/328-324/328 ILK: pass/total=328/330-330/330 IVB: pass/total=545/546-544/546 SNB: pass/total=558/563-558/563 HSW: pass/total=574/578-573/578 BDW: pass/total=435/435-434/435 -Detailed- test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...-result_with_patch_applied(count, machine_id)... BYT: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc-lut, NSPT(1, M29)PASS(9, M36M29) - NSPT(1, M36)PASS(3, M36) PNV: Intel_gpu_tools, igt_gem_concurrent_blit_gpu-bcs-early-read, PASS(7, M23M24) - DMESG_WARN(1, M23)PASS(3, M23) PNV: Intel_gpu_tools, igt_gem_mmap_offset_exhaustion, DMESG_WARN(2, M23M24)PASS(14, M24M23M7) - PASS(4, M23) PNV: Intel_gpu_tools, igt_gem_unref_active_buffers, DMESG_WARN(2, M23)PASS(14, M24M23M7) - PASS(4, M23) ILK: Intel_gpu_tools, igt_kms_render_gpu-blit, DMESG_WARN(1, M26)PASS(15, M6M26M37) - PASS(4, M6) ILK: Intel_gpu_tools, igt_kms_flip_wf_vblank-vs-dpms-interruptible, DMESG_WARN(1, M26)PASS(15, M6M26M37) - PASS(4, M6) IVB: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc, NSPT(2, M4M34)PASS(5, M34M4) - NSPT(2, M34)PASS(2, M34) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-random, PASS(4, M35M22) - DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-sliding, DMESG_WARN(1, M35)PASS(3, M22) - PASS(4, M22) HSW: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc, NSPT(4, M39M20M40)PASS(9, M40M39M20) - NSPT(2, M20)PASS(2, M20) BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, PASS(10, M30M28) - DMESG_WARN(1, M30)PASS(3, M30) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
