Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
Op 30-08-18 om 14:41 schreef Juha-Pekka Heikkila: > Preparations for enabling P010, P012 and P016 formats. These > formats will extend NV12 for larger bit depths. > > (Sharma, Swati2): removed unnecessary checks, changed debug error message > to be more generic. > > Signed-off-by: Juha-Pekka Heikkila > --- > drivers/gpu/drm/i915/intel_atomic.c | 3 +-- > drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- > drivers/gpu/drm/i915/intel_display.c | 41 > +-- > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 19 +++--- > drivers/gpu/drm/i915/intel_sprite.c | 18 +- > 6 files changed, 63 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_atomic.c > b/drivers/gpu/drm/i915/intel_atomic.c > index b04952b..ab76b72 100644 > --- a/drivers/gpu/drm/i915/intel_atomic.c > +++ b/drivers/gpu/drm/i915/intel_atomic.c > @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private > *dev_priv, > /* set scaler mode */ > if ((INTEL_GEN(dev_priv) >= 9) && > plane_state && plane_state->base.fb && > - plane_state->base.fb->format->format == > - DRM_FORMAT_NV12) { > + is_planar_yuv_format(plane_state->base.fb->format->format)) > { > if (INTEL_GEN(dev_priv) == 9 && > !IS_GEMINILAKE(dev_priv) && > !IS_SKYLAKE(dev_priv)) > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c > b/drivers/gpu/drm/i915/intel_atomic_plane.c > index fa7df5f..d64d993 100644 > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c > @@ -184,7 +184,7 @@ int intel_plane_atomic_check_with_state(const struct > intel_crtc_state *old_crtc_ > else > crtc_state->active_planes &= ~BIT(intel_plane->id); > > - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12) > + if (state->visible && is_planar_yuv_format(state->fb->format->format)) > crtc_state->nv12_planes |= BIT(intel_plane->id); > else > crtc_state->nv12_planes &= ~BIT(intel_plane->id); > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 4bb46f2..43efeb4 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2672,6 +2672,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, > bool alpha) > return DRM_FORMAT_RGB565; > case PLANE_CTL_FORMAT_NV12: > return DRM_FORMAT_NV12; > + case PLANE_CTL_FORMAT_P010: > + return DRM_FORMAT_P010; > + case PLANE_CTL_FORMAT_P012: > + return DRM_FORMAT_P012; > + case PLANE_CTL_FORMAT_P016: > + return DRM_FORMAT_P016; > default: > case PLANE_CTL_FORMAT_XRGB_: > if (rgb_order) { > @@ -3187,7 +3193,7 @@ int skl_check_plane_surface(const struct > intel_crtc_state *crtc_state, >* Handle the AUX surface first since >* the main surface setup depends on it. >*/ > - if (fb->format->format == DRM_FORMAT_NV12) { > + if (is_planar_yuv_format(fb->format->format)) { > ret = skl_check_nv12_surface(crtc_state, plane_state); > if (ret) > return ret; > @@ -3511,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) > return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; > case DRM_FORMAT_NV12: > return PLANE_CTL_FORMAT_NV12; > + case DRM_FORMAT_P010: > + return PLANE_CTL_FORMAT_P010; > + case DRM_FORMAT_P012: > + return PLANE_CTL_FORMAT_P012; > + case DRM_FORMAT_P016: > + return PLANE_CTL_FORMAT_P016; > default: > MISSING_CASE(pixel_format); > } > @@ -4812,8 +4824,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, > bool force_detach, > need_scaling = src_w != dst_w || src_h != dst_h; > > if (plane_scaler_check) > - if (pixel_format == DRM_FORMAT_NV12) > - need_scaling = true; > + need_scaling = is_planar_yuv_format(pixel_format); Should this be |=, or we disable all scaling ever? ~Maarten > > if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) > need_scaling = true; > @@ -4854,9 +4865,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, > bool force_detach, > return 0; > } > > - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 && > + if (plane_scaler_check && is_planar_yuv_format(pixel_format) && > (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { > - DRM_DEBUG_KMS("NV12: src dimensions not met\n"); > + DRM_DEBUG_KMS("planar yuv: src dimensions not
Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
On Thu, Aug 30, 2018 at 03:41:13PM +0300, Juha-Pekka Heikkila wrote: > Preparations for enabling P010, P012 and P016 formats. These > formats will extend NV12 for larger bit depths. > > (Sharma, Swati2): removed unnecessary checks, changed debug error message > to be more generic. > > Signed-off-by: Juha-Pekka Heikkila > --- > drivers/gpu/drm/i915/intel_atomic.c | 3 +-- > drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- > drivers/gpu/drm/i915/intel_display.c | 41 > +-- > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 19 +++--- > drivers/gpu/drm/i915/intel_sprite.c | 18 +- > 6 files changed, 63 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_atomic.c > b/drivers/gpu/drm/i915/intel_atomic.c > index b04952b..ab76b72 100644 > --- a/drivers/gpu/drm/i915/intel_atomic.c > +++ b/drivers/gpu/drm/i915/intel_atomic.c > @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private > *dev_priv, > /* set scaler mode */ > if ((INTEL_GEN(dev_priv) >= 9) && > plane_state && plane_state->base.fb && > - plane_state->base.fb->format->format == > - DRM_FORMAT_NV12) { > + is_planar_yuv_format(plane_state->base.fb->format->format)) > { Since there is .is_yuv now it might make sense to stick this into some common place (drm_fourcc.h perhaps) as something like 'is_yuv && num_planes > 1' > if (INTEL_GEN(dev_priv) == 9 && > !IS_GEMINILAKE(dev_priv) && > !IS_SKYLAKE(dev_priv)) > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c > b/drivers/gpu/drm/i915/intel_atomic_plane.c > index fa7df5f..d64d993 100644 > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c > @@ -184,7 +184,7 @@ int intel_plane_atomic_check_with_state(const struct > intel_crtc_state *old_crtc_ > else > crtc_state->active_planes &= ~BIT(intel_plane->id); > > - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12) > + if (state->visible && is_planar_yuv_format(state->fb->format->format)) > crtc_state->nv12_planes |= BIT(intel_plane->id); > else > crtc_state->nv12_planes &= ~BIT(intel_plane->id); > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 4bb46f2..43efeb4 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2672,6 +2672,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, > bool alpha) > return DRM_FORMAT_RGB565; > case PLANE_CTL_FORMAT_NV12: > return DRM_FORMAT_NV12; > + case PLANE_CTL_FORMAT_P010: > + return DRM_FORMAT_P010; > + case PLANE_CTL_FORMAT_P012: > + return DRM_FORMAT_P012; > + case PLANE_CTL_FORMAT_P016: > + return DRM_FORMAT_P016; > default: > case PLANE_CTL_FORMAT_XRGB_: > if (rgb_order) { > @@ -3187,7 +3193,7 @@ int skl_check_plane_surface(const struct > intel_crtc_state *crtc_state, >* Handle the AUX surface first since >* the main surface setup depends on it. >*/ > - if (fb->format->format == DRM_FORMAT_NV12) { > + if (is_planar_yuv_format(fb->format->format)) { > ret = skl_check_nv12_surface(crtc_state, plane_state); > if (ret) > return ret; > @@ -3511,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) > return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; > case DRM_FORMAT_NV12: > return PLANE_CTL_FORMAT_NV12; > + case DRM_FORMAT_P010: > + return PLANE_CTL_FORMAT_P010; > + case DRM_FORMAT_P012: > + return PLANE_CTL_FORMAT_P012; > + case DRM_FORMAT_P016: > + return PLANE_CTL_FORMAT_P016; > default: > MISSING_CASE(pixel_format); > } > @@ -4812,8 +4824,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, > bool force_detach, > need_scaling = src_w != dst_w || src_h != dst_h; > > if (plane_scaler_check) > - if (pixel_format == DRM_FORMAT_NV12) > - need_scaling = true; > + need_scaling = is_planar_yuv_format(pixel_format); > > if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) > need_scaling = true; > @@ -4854,9 +4865,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, > bool force_detach, > return 0; > } > > - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 && > + if (plane_scaler_check && is_planar_yuv_format(pixel_format) && > (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { > -
[Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. (Sharma, Swati2): removed unnecessary checks, changed debug error message to be more generic. Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/intel_atomic.c | 3 +-- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 41 +-- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 19 +++--- drivers/gpu/drm/i915/intel_sprite.c | 18 +- 6 files changed, 63 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index b04952b..ab76b72 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, /* set scaler mode */ if ((INTEL_GEN(dev_priv) >= 9) && plane_state && plane_state->base.fb && - plane_state->base.fb->format->format == - DRM_FORMAT_NV12) { + is_planar_yuv_format(plane_state->base.fb->format->format)) { if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && !IS_SKYLAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index fa7df5f..d64d993 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -184,7 +184,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ else crtc_state->active_planes &= ~BIT(intel_plane->id); - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12) + if (state->visible && is_planar_yuv_format(state->fb->format->format)) crtc_state->nv12_planes |= BIT(intel_plane->id); else crtc_state->nv12_planes &= ~BIT(intel_plane->id); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4bb46f2..43efeb4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2672,6 +2672,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) return DRM_FORMAT_RGB565; case PLANE_CTL_FORMAT_NV12: return DRM_FORMAT_NV12; + case PLANE_CTL_FORMAT_P010: + return DRM_FORMAT_P010; + case PLANE_CTL_FORMAT_P012: + return DRM_FORMAT_P012; + case PLANE_CTL_FORMAT_P016: + return DRM_FORMAT_P016; default: case PLANE_CTL_FORMAT_XRGB_: if (rgb_order) { @@ -3187,7 +3193,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state, * Handle the AUX surface first since * the main surface setup depends on it. */ - if (fb->format->format == DRM_FORMAT_NV12) { + if (is_planar_yuv_format(fb->format->format)) { ret = skl_check_nv12_surface(crtc_state, plane_state); if (ret) return ret; @@ -3511,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; case DRM_FORMAT_NV12: return PLANE_CTL_FORMAT_NV12; + case DRM_FORMAT_P010: + return PLANE_CTL_FORMAT_P010; + case DRM_FORMAT_P012: + return PLANE_CTL_FORMAT_P012; + case DRM_FORMAT_P016: + return PLANE_CTL_FORMAT_P016; default: MISSING_CASE(pixel_format); } @@ -4812,8 +4824,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, need_scaling = src_w != dst_w || src_h != dst_h; if (plane_scaler_check) - if (pixel_format == DRM_FORMAT_NV12) - need_scaling = true; + need_scaling = is_planar_yuv_format(pixel_format); if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) need_scaling = true; @@ -4854,9 +4865,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, return 0; } - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 && + if (plane_scaler_check && is_planar_yuv_format(pixel_format) && (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { - DRM_DEBUG_KMS("NV12: src dimensions not met\n"); + DRM_DEBUG_KMS("planar yuv: src dimensions not met\n"); return -EINVAL; } @@ -4959,6 +4970,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY:
Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
On 27.08.2018 14:28, Maarten Lankhorst wrote: Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila: Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_atomic.c | 3 +- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 46 +++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 19 ++--- drivers/gpu/drm/i915/intel_sprite.c | 18 +++- 6 files changed, 69 insertions(+), 20 deletions(-) For patches 2, 3, 4: Acked-by: Jani Nikula #irc, for merging through drm-misc-next. Are you ok with Swati Sharma's comment on patch 4? I can fix it up when committing. I'm all ok with Swati Sharma's comment. /Juha-Pekka diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index b04952b..ab76b72 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, /* set scaler mode */ if ((INTEL_GEN(dev_priv) >= 9) && plane_state && plane_state->base.fb && - plane_state->base.fb->format->format == - DRM_FORMAT_NV12) { + is_planar_yuv_format(plane_state->base.fb->format->format)) { if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && !IS_SKYLAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index dcba645..58b2fc6 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ else crtc_state->active_planes &= ~BIT(intel_plane->id); - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12) + if (state->visible && is_planar_yuv_format(state->fb->format->format)) crtc_state->nv12_planes |= BIT(intel_plane->id); else crtc_state->nv12_planes &= ~BIT(intel_plane->id); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 690e1e8..80ce742 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) return DRM_FORMAT_RGB565; case PLANE_CTL_FORMAT_NV12: return DRM_FORMAT_NV12; + case PLANE_CTL_FORMAT_P010: + return DRM_FORMAT_P010; + case PLANE_CTL_FORMAT_P012: + return DRM_FORMAT_P012; + case PLANE_CTL_FORMAT_P016: + return DRM_FORMAT_P016; default: case PLANE_CTL_FORMAT_XRGB_: if (rgb_order) { @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state, * Handle the AUX surface first since * the main surface setup depends on it. */ - if (fb->format->format == DRM_FORMAT_NV12) { + if (is_planar_yuv_format(fb->format->format)) { ret = skl_check_nv12_surface(crtc_state, plane_state); if (ret) return ret; @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; case DRM_FORMAT_NV12: return PLANE_CTL_FORMAT_NV12; + case DRM_FORMAT_P010: + return PLANE_CTL_FORMAT_P010; + case DRM_FORMAT_P012: + return PLANE_CTL_FORMAT_P012; + case DRM_FORMAT_P016: + return PLANE_CTL_FORMAT_P016; default: MISSING_CASE(pixel_format); } @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, need_scaling = src_w != dst_w || src_h != dst_h; if (plane_scaler_check) - if (pixel_format == DRM_FORMAT_NV12) - need_scaling = true; + need_scaling = is_planar_yuv_format(pixel_format); if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) need_scaling = true; @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, return 0; } - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 && + if (plane_scaler_check && is_planar_yuv_format(pixel_format) && (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { DRM_DEBUG_KMS("NV12: src dimensions not met\n");
Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila: > Preparations for enabling P010, P012 and P016 formats. These > formats will extend NV12 for larger bit depths. > > Signed-off-by: Juha-Pekka Heikkila > Reviewed-by: Maarten Lankhorst > --- > drivers/gpu/drm/i915/intel_atomic.c | 3 +- > drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- > drivers/gpu/drm/i915/intel_display.c | 46 > +++ > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 19 ++--- > drivers/gpu/drm/i915/intel_sprite.c | 18 +++- > 6 files changed, 69 insertions(+), 20 deletions(-) For patches 2, 3, 4: Acked-by: Jani Nikula #irc, for merging through drm-misc-next. Are you ok with Swati Sharma's comment on patch 4? I can fix it up when committing. > diff --git a/drivers/gpu/drm/i915/intel_atomic.c > b/drivers/gpu/drm/i915/intel_atomic.c > index b04952b..ab76b72 100644 > --- a/drivers/gpu/drm/i915/intel_atomic.c > +++ b/drivers/gpu/drm/i915/intel_atomic.c > @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private > *dev_priv, > /* set scaler mode */ > if ((INTEL_GEN(dev_priv) >= 9) && > plane_state && plane_state->base.fb && > - plane_state->base.fb->format->format == > - DRM_FORMAT_NV12) { > + is_planar_yuv_format(plane_state->base.fb->format->format)) > { > if (INTEL_GEN(dev_priv) == 9 && > !IS_GEMINILAKE(dev_priv) && > !IS_SKYLAKE(dev_priv)) > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c > b/drivers/gpu/drm/i915/intel_atomic_plane.c > index dcba645..58b2fc6 100644 > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c > @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct > intel_crtc_state *old_crtc_ > else > crtc_state->active_planes &= ~BIT(intel_plane->id); > > - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12) > + if (state->visible && is_planar_yuv_format(state->fb->format->format)) > crtc_state->nv12_planes |= BIT(intel_plane->id); > else > crtc_state->nv12_planes &= ~BIT(intel_plane->id); > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 690e1e8..80ce742 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, > bool alpha) > return DRM_FORMAT_RGB565; > case PLANE_CTL_FORMAT_NV12: > return DRM_FORMAT_NV12; > + case PLANE_CTL_FORMAT_P010: > + return DRM_FORMAT_P010; > + case PLANE_CTL_FORMAT_P012: > + return DRM_FORMAT_P012; > + case PLANE_CTL_FORMAT_P016: > + return DRM_FORMAT_P016; > default: > case PLANE_CTL_FORMAT_XRGB_: > if (rgb_order) { > @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct > intel_crtc_state *crtc_state, >* Handle the AUX surface first since >* the main surface setup depends on it. >*/ > - if (fb->format->format == DRM_FORMAT_NV12) { > + if (is_planar_yuv_format(fb->format->format)) { > ret = skl_check_nv12_surface(crtc_state, plane_state); > if (ret) > return ret; > @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) > return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; > case DRM_FORMAT_NV12: > return PLANE_CTL_FORMAT_NV12; > + case DRM_FORMAT_P010: > + return PLANE_CTL_FORMAT_P010; > + case DRM_FORMAT_P012: > + return PLANE_CTL_FORMAT_P012; > + case DRM_FORMAT_P016: > + return PLANE_CTL_FORMAT_P016; > default: > MISSING_CASE(pixel_format); > } > @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, > bool force_detach, > need_scaling = src_w != dst_w || src_h != dst_h; > > if (plane_scaler_check) > - if (pixel_format == DRM_FORMAT_NV12) > - need_scaling = true; > + need_scaling = is_planar_yuv_format(pixel_format); > > if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) > need_scaling = true; > @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, > bool force_detach, > return 0; > } > > - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 && > + if (plane_scaler_check && is_planar_yuv_format(pixel_format) && > (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { > DRM_DEBUG_KMS("NV12: src dimensions not met\n"); > return
Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
On 21.08.2018 17:26, Sharma, Swati2 wrote: On 16-Aug-18 6:25 PM, Juha-Pekka Heikkila wrote: Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_atomic.c | 3 +- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 46 +++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 19 ++--- drivers/gpu/drm/i915/intel_sprite.c | 18 +++- 6 files changed, 69 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index b04952b..ab76b72 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, /* set scaler mode */ if ((INTEL_GEN(dev_priv) >= 9) && plane_state && plane_state->base.fb && - plane_state->base.fb->format->format == - DRM_FORMAT_NV12) { + is_planar_yuv_format(plane_state->base.fb->format->format)) { if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && !IS_SKYLAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index dcba645..58b2fc6 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ else crtc_state->active_planes &= ~BIT(intel_plane->id); - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12) + if (state->visible && is_planar_yuv_format(state->fb->format->format)) crtc_state->nv12_planes |= BIT(intel_plane->id); else crtc_state->nv12_planes &= ~BIT(intel_plane->id); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 690e1e8..80ce742 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) return DRM_FORMAT_RGB565; case PLANE_CTL_FORMAT_NV12: return DRM_FORMAT_NV12; + case PLANE_CTL_FORMAT_P010: + return DRM_FORMAT_P010; + case PLANE_CTL_FORMAT_P012: + return DRM_FORMAT_P012; + case PLANE_CTL_FORMAT_P016: + return DRM_FORMAT_P016; default: case PLANE_CTL_FORMAT_XRGB_: if (rgb_order) { @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state, * Handle the AUX surface first since * the main surface setup depends on it. */ - if (fb->format->format == DRM_FORMAT_NV12) { + if (is_planar_yuv_format(fb->format->format)) { ret = skl_check_nv12_surface(crtc_state, plane_state); if (ret) return ret; @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; case DRM_FORMAT_NV12: return PLANE_CTL_FORMAT_NV12; + case DRM_FORMAT_P010: + return PLANE_CTL_FORMAT_P010; + case DRM_FORMAT_P012: + return PLANE_CTL_FORMAT_P012; + case DRM_FORMAT_P016: + return PLANE_CTL_FORMAT_P016; default: MISSING_CASE(pixel_format); } @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, need_scaling = src_w != dst_w || src_h != dst_h; if (plane_scaler_check) - if (pixel_format == DRM_FORMAT_NV12) - need_scaling = true; + need_scaling = is_planar_yuv_format(pixel_format); if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) need_scaling = true; @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, return 0; } - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 && + if (plane_scaler_check && is_planar_yuv_format(pixel_format) && (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { DRM_DEBUG_KMS("NV12: src dimensions not met\n"); return -EINVAL; @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_P010: + case DRM_FORMAT_P012: + case DRM_FORMAT_P016: break; default: DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", @@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, * or * cdclk/crtc_clock
Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
On 16-Aug-18 6:25 PM, Juha-Pekka Heikkila wrote: Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_atomic.c | 3 +- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 46 +++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 19 ++--- drivers/gpu/drm/i915/intel_sprite.c | 18 +++- 6 files changed, 69 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index b04952b..ab76b72 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, /* set scaler mode */ if ((INTEL_GEN(dev_priv) >= 9) && plane_state && plane_state->base.fb && - plane_state->base.fb->format->format == - DRM_FORMAT_NV12) { + is_planar_yuv_format(plane_state->base.fb->format->format)) { if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && !IS_SKYLAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index dcba645..58b2fc6 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ else crtc_state->active_planes &= ~BIT(intel_plane->id); - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12) + if (state->visible && is_planar_yuv_format(state->fb->format->format)) crtc_state->nv12_planes |= BIT(intel_plane->id); else crtc_state->nv12_planes &= ~BIT(intel_plane->id); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 690e1e8..80ce742 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) return DRM_FORMAT_RGB565; case PLANE_CTL_FORMAT_NV12: return DRM_FORMAT_NV12; + case PLANE_CTL_FORMAT_P010: + return DRM_FORMAT_P010; + case PLANE_CTL_FORMAT_P012: + return DRM_FORMAT_P012; + case PLANE_CTL_FORMAT_P016: + return DRM_FORMAT_P016; default: case PLANE_CTL_FORMAT_XRGB_: if (rgb_order) { @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state, * Handle the AUX surface first since * the main surface setup depends on it. */ - if (fb->format->format == DRM_FORMAT_NV12) { + if (is_planar_yuv_format(fb->format->format)) { ret = skl_check_nv12_surface(crtc_state, plane_state); if (ret) return ret; @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; case DRM_FORMAT_NV12: return PLANE_CTL_FORMAT_NV12; + case DRM_FORMAT_P010: + return PLANE_CTL_FORMAT_P010; + case DRM_FORMAT_P012: + return PLANE_CTL_FORMAT_P012; + case DRM_FORMAT_P016: + return PLANE_CTL_FORMAT_P016; default: MISSING_CASE(pixel_format); } @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, need_scaling = src_w != dst_w || src_h != dst_h; if (plane_scaler_check) - if (pixel_format == DRM_FORMAT_NV12) - need_scaling = true; + need_scaling = is_planar_yuv_format(pixel_format); if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) need_scaling = true; @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, return 0; } - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 && + if (plane_scaler_check && is_planar_yuv_format(pixel_format) && (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { DRM_DEBUG_KMS("NV12: src dimensions not met\n"); return -EINVAL; @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_P010: + case DRM_FORMAT_P012: + case
[Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_atomic.c | 3 +- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 46 +++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 19 ++--- drivers/gpu/drm/i915/intel_sprite.c | 18 +++- 6 files changed, 69 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index b04952b..ab76b72 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, /* set scaler mode */ if ((INTEL_GEN(dev_priv) >= 9) && plane_state && plane_state->base.fb && - plane_state->base.fb->format->format == - DRM_FORMAT_NV12) { + is_planar_yuv_format(plane_state->base.fb->format->format)) { if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && !IS_SKYLAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index dcba645..58b2fc6 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ else crtc_state->active_planes &= ~BIT(intel_plane->id); - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12) + if (state->visible && is_planar_yuv_format(state->fb->format->format)) crtc_state->nv12_planes |= BIT(intel_plane->id); else crtc_state->nv12_planes &= ~BIT(intel_plane->id); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 690e1e8..80ce742 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) return DRM_FORMAT_RGB565; case PLANE_CTL_FORMAT_NV12: return DRM_FORMAT_NV12; + case PLANE_CTL_FORMAT_P010: + return DRM_FORMAT_P010; + case PLANE_CTL_FORMAT_P012: + return DRM_FORMAT_P012; + case PLANE_CTL_FORMAT_P016: + return DRM_FORMAT_P016; default: case PLANE_CTL_FORMAT_XRGB_: if (rgb_order) { @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state, * Handle the AUX surface first since * the main surface setup depends on it. */ - if (fb->format->format == DRM_FORMAT_NV12) { + if (is_planar_yuv_format(fb->format->format)) { ret = skl_check_nv12_surface(crtc_state, plane_state); if (ret) return ret; @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; case DRM_FORMAT_NV12: return PLANE_CTL_FORMAT_NV12; + case DRM_FORMAT_P010: + return PLANE_CTL_FORMAT_P010; + case DRM_FORMAT_P012: + return PLANE_CTL_FORMAT_P012; + case DRM_FORMAT_P016: + return PLANE_CTL_FORMAT_P016; default: MISSING_CASE(pixel_format); } @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, need_scaling = src_w != dst_w || src_h != dst_h; if (plane_scaler_check) - if (pixel_format == DRM_FORMAT_NV12) - need_scaling = true; + need_scaling = is_planar_yuv_format(pixel_format); if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) need_scaling = true; @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, return 0; } - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 && + if (plane_scaler_check && is_planar_yuv_format(pixel_format) && (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { DRM_DEBUG_KMS("NV12: src dimensions not met\n"); return -EINVAL; @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_P010: + case DRM_FORMAT_P012: + case DRM_FORMAT_P016: break;
[Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/intel_atomic.c | 3 +- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 48 ++- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 19 ++-- drivers/gpu/drm/i915/intel_sprite.c | 21 +- 6 files changed, 73 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index 61ddb58..d42624b 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -332,8 +332,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, /* set scaler mode */ if ((INTEL_GEN(dev_priv) >= 9) && plane_state && plane_state->base.fb && - plane_state->base.fb->format->format == - DRM_FORMAT_NV12) { + is_planar_yuv_format(plane_state->base.fb->format->format)) { if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && !IS_SKYLAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index 6d06878..aca3bef 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -188,7 +188,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ else crtc_state->active_planes &= ~BIT(intel_plane->id); - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12) + if (state->visible && is_planar_yuv_format(state->fb->format->format)) crtc_state->nv12_planes |= BIT(intel_plane->id); else crtc_state->nv12_planes &= ~BIT(intel_plane->id); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8d4c9e2..236b83f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2664,6 +2664,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) return DRM_FORMAT_RGB565; case PLANE_CTL_FORMAT_NV12: return DRM_FORMAT_NV12; + case PLANE_CTL_FORMAT_P010: + return DRM_FORMAT_P010; + case PLANE_CTL_FORMAT_P012: + return DRM_FORMAT_P012; + case PLANE_CTL_FORMAT_P016: + return DRM_FORMAT_P016; default: case PLANE_CTL_FORMAT_XRGB_: if (rgb_order) { @@ -3180,7 +3186,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state, * Handle the AUX surface first since * the main surface setup depends on it. */ - if (fb->format->format == DRM_FORMAT_NV12) { + if (is_planar_yuv_format(fb->format->format)) { ret = skl_check_nv12_surface(crtc_state, plane_state); if (ret) return ret; @@ -3496,6 +3502,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; case DRM_FORMAT_NV12: return PLANE_CTL_FORMAT_NV12; + case DRM_FORMAT_P010: + return PLANE_CTL_FORMAT_P010; + case DRM_FORMAT_P012: + return PLANE_CTL_FORMAT_P012; + case DRM_FORMAT_P016: + return PLANE_CTL_FORMAT_P016; default: MISSING_CASE(pixel_format); } @@ -3647,7 +3659,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format); if (intel_format_is_yuv(fb->format->format)) { - if (fb->format->format == DRM_FORMAT_NV12) { + if (is_planar_yuv_format(fb->format->format)) { plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; goto out; @@ -4769,8 +4781,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, need_scaling = src_w != dst_w || src_h != dst_h; if (plane_scaler_check) - if (pixel_format == DRM_FORMAT_NV12) - need_scaling = true; + need_scaling = is_planar_yuv_format(pixel_format); if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) need_scaling = true; @@ -4811,7 +4822,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, return 0; } - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 && + if (plane_scaler_check && is_planar_yuv_format(pixel_format) && (src_h <