Re: [Intel-gfx] [PATCH 4/4] drm/i915: move sideband regs to vlv_sideband_reg.h
On Tue, 14 Nov 2023, Ville Syrjälä wrote:
> On Mon, Nov 13, 2023 at 06:47:11PM +0200, Jani Nikula wrote:
>> Move the VLV/CHV sideband doorbell and data/addr MMIO registers as well
>> as the DPIO register definitions to vlv_sideband_reg.h.
>
> I have patches sitting in a branch to extract {vlv,bxt}_dpio_phy_regs.h
> instead. I think that split makes more sense in terms of how the
> hardware is structured.
I don't disagree. I'll drop this patch, please rebase yours once 1-3
have been merged. I'll send v2 of them shortly.
BR,
Jani.
>
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 374 ---
>> drivers/gpu/drm/i915/vlv_sideband_reg.h | 377
>> 2 files changed, 377 insertions(+), 374 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 27dc903f0553..cd3974127b66 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -158,386 +158,12 @@
>> #define DEBUG_RESET_RENDER (1 << 8)
>> #define DEBUG_RESET_DISPLAY(1 << 9)
>>
>> -/*
>> - * IOSF sideband
>> - */
>> -#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE
>> + 0x2100)
>> -#define IOSF_DEVFN_SHIFT 24
>> -#define IOSF_OPCODE_SHIFT 16
>> -#define IOSF_PORT_SHIFT 8
>> -#define IOSF_BYTE_ENABLES_SHIFT 4
>> -#define IOSF_BAR_SHIFT1
>> -#define IOSF_SB_BUSY (1 << 0)
>> -#define IOSF_PORT_BUNIT 0x03
>> -#define IOSF_PORT_PUNIT 0x04
>> -#define IOSF_PORT_NC 0x11
>> -#define IOSF_PORT_DPIO0x12
>> -#define IOSF_PORT_GPIO_NC 0x13
>> -#define IOSF_PORT_CCK 0x14
>> -#define IOSF_PORT_DPIO_2 0x1a
>> -#define IOSF_PORT_FLISDSI 0x1b
>> -#define IOSF_PORT_GPIO_SC 0x48
>> -#define IOSF_PORT_GPIO_SUS0xa8
>> -#define IOSF_PORT_CCU 0xa9
>> -#define CHV_IOSF_PORT_GPIO_N 0x13
>> -#define CHV_IOSF_PORT_GPIO_SE 0x48
>> -#define CHV_IOSF_PORT_GPIO_E 0xa8
>> -#define CHV_IOSF_PORT_GPIO_SW 0xb2
>> -#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE
>> + 0x2104)
>> -#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE
>> + 0x2108)
>> -
>> -/* DPIO registers */
>> -#define DPIO_DEVFN 0
>> -
>> #define DPIO_CTL_MMIO(VLV_DISPLAY_BASE + 0x2110)
>> #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27
>> */
>> #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27
>> */
>> #define DPIO_SFR_BYPASS(1 << 1)
>> #define DPIO_CMNRST(1 << 0)
>>
>> -/*
>> - * Per pipe/PLL DPIO regs
>> - */
>> -#define _VLV_PLL_DW3_CH00x800c
>> -#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
>> -#define DPIO_POST_DIV_DAC 0
>> -#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
>> -#define DPIO_POST_DIV_LVDS1 2
>> -#define DPIO_POST_DIV_LVDS2 3
>> -#define DPIO_K_SHIFT (24) /* 4 bits */
>> -#define DPIO_P1_SHIFT (21) /* 3 bits */
>> -#define DPIO_P2_SHIFT (16) /* 5 bits */
>> -#define DPIO_N_SHIFT (12) /* 4 bits */
>> -#define DPIO_ENABLE_CALIBRATION (1 << 11)
>> -#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
>> -#define DPIO_M2DIV_MASK 0xff
>> -#define _VLV_PLL_DW3_CH10x802c
>> -#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
>> -
>> -#define _VLV_PLL_DW5_CH00x8014
>> -#define DPIO_REFSEL_OVERRIDE 27
>> -#define DPIO_PLL_MODESEL_SHIFT24 /* 3 bits */
>> -#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
>> -#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
>> -#define DPIO_PLL_REFCLK_SEL_MASK 3
>> -#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
>> -#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
>> -#define _VLV_PLL_DW5_CH10x8034
>> -#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
>> -
>> -#define _VLV_PLL_DW7_CH00x801c
>> -#define _VLV_PLL_DW7_CH10x803c
>> -#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
>> -
>> -#define _VLV_PLL_DW8_CH00x8040
>> -#define _VLV_PLL_DW8_CH10x8060
>> -#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
>> -
>> -#define VLV_PLL_DW9_BCAST 0xc044
>> -#define _VLV_PLL_DW9_CH0
Re: [Intel-gfx] [PATCH 4/4] drm/i915: move sideband regs to vlv_sideband_reg.h
On Mon, Nov 13, 2023 at 06:47:11PM +0200, Jani Nikula wrote:
> Move the VLV/CHV sideband doorbell and data/addr MMIO registers as well
> as the DPIO register definitions to vlv_sideband_reg.h.
I have patches sitting in a branch to extract {vlv,bxt}_dpio_phy_regs.h
instead. I think that split makes more sense in terms of how the
hardware is structured.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 374 ---
> drivers/gpu/drm/i915/vlv_sideband_reg.h | 377
> 2 files changed, 377 insertions(+), 374 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 27dc903f0553..cd3974127b66 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -158,386 +158,12 @@
> #define DEBUG_RESET_RENDER (1 << 8)
> #define DEBUG_RESET_DISPLAY (1 << 9)
>
> -/*
> - * IOSF sideband
> - */
> -#define VLV_IOSF_DOORBELL_REQ_MMIO(VLV_DISPLAY_BASE
> + 0x2100)
> -#define IOSF_DEVFN_SHIFT 24
> -#define IOSF_OPCODE_SHIFT 16
> -#define IOSF_PORT_SHIFT8
> -#define IOSF_BYTE_ENABLES_SHIFT4
> -#define IOSF_BAR_SHIFT 1
> -#define IOSF_SB_BUSY (1 << 0)
> -#define IOSF_PORT_BUNIT0x03
> -#define IOSF_PORT_PUNIT0x04
> -#define IOSF_PORT_NC 0x11
> -#define IOSF_PORT_DPIO 0x12
> -#define IOSF_PORT_GPIO_NC 0x13
> -#define IOSF_PORT_CCK 0x14
> -#define IOSF_PORT_DPIO_2 0x1a
> -#define IOSF_PORT_FLISDSI 0x1b
> -#define IOSF_PORT_GPIO_SC 0x48
> -#define IOSF_PORT_GPIO_SUS 0xa8
> -#define IOSF_PORT_CCU 0xa9
> -#define CHV_IOSF_PORT_GPIO_N 0x13
> -#define CHV_IOSF_PORT_GPIO_SE 0x48
> -#define CHV_IOSF_PORT_GPIO_E 0xa8
> -#define CHV_IOSF_PORT_GPIO_SW 0xb2
> -#define VLV_IOSF_DATA_MMIO(VLV_DISPLAY_BASE
> + 0x2104)
> -#define VLV_IOSF_ADDR_MMIO(VLV_DISPLAY_BASE
> + 0x2108)
> -
> -/* DPIO registers */
> -#define DPIO_DEVFN 0
> -
> #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
> #define DPIO_MODSEL1(1 << 3) /* if ref clk b == 27
> */
> #define DPIO_MODSEL0(1 << 2) /* if ref clk a == 27
> */
> #define DPIO_SFR_BYPASS (1 << 1)
> #define DPIO_CMNRST (1 << 0)
>
> -/*
> - * Per pipe/PLL DPIO regs
> - */
> -#define _VLV_PLL_DW3_CH0 0x800c
> -#define DPIO_POST_DIV_SHIFT(28) /* 3 bits */
> -#define DPIO_POST_DIV_DAC 0
> -#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
> -#define DPIO_POST_DIV_LVDS12
> -#define DPIO_POST_DIV_LVDS23
> -#define DPIO_K_SHIFT (24) /* 4 bits */
> -#define DPIO_P1_SHIFT (21) /* 3 bits */
> -#define DPIO_P2_SHIFT (16) /* 5 bits */
> -#define DPIO_N_SHIFT (12) /* 4 bits */
> -#define DPIO_ENABLE_CALIBRATION(1 << 11)
> -#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
> -#define DPIO_M2DIV_MASK0xff
> -#define _VLV_PLL_DW3_CH1 0x802c
> -#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
> -
> -#define _VLV_PLL_DW5_CH0 0x8014
> -#define DPIO_REFSEL_OVERRIDE 27
> -#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
> -#define DPIO_BIAS_CURRENT_CTL_SHIFT21 /* 3 bits, always 0x7 */
> -#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
> -#define DPIO_PLL_REFCLK_SEL_MASK 3
> -#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
> -#define DPIO_CLK_BIAS_CTL_SHIFT8 /* always set to 0x5 */
> -#define _VLV_PLL_DW5_CH1 0x8034
> -#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
> -
> -#define _VLV_PLL_DW7_CH0 0x801c
> -#define _VLV_PLL_DW7_CH1 0x803c
> -#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
> -
> -#define _VLV_PLL_DW8_CH0 0x8040
> -#define _VLV_PLL_DW8_CH1 0x8060
> -#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
> -
> -#define VLV_PLL_DW9_BCAST0xc044
> -#define _VLV_PLL_DW9_CH0 0x8044
> -#define _VLV_PLL_DW9_CH1 0x8064
> -#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
> -
> -#define _VLV_PLL_DW10_CH00x8048
> -#define _VLV_PLL_DW10_CH10x8068
> -#define
[Intel-gfx] [PATCH 4/4] drm/i915: move sideband regs to vlv_sideband_reg.h
Move the VLV/CHV sideband doorbell and data/addr MMIO registers as well as the DPIO register definitions to vlv_sideband_reg.h. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 374 --- drivers/gpu/drm/i915/vlv_sideband_reg.h | 377 2 files changed, 377 insertions(+), 374 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 27dc903f0553..cd3974127b66 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -158,386 +158,12 @@ #define DEBUG_RESET_RENDER(1 << 8) #define DEBUG_RESET_DISPLAY (1 << 9) -/* - * IOSF sideband - */ -#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) -#define IOSF_DEVFN_SHIFT 24 -#define IOSF_OPCODE_SHIFT16 -#define IOSF_PORT_SHIFT 8 -#define IOSF_BYTE_ENABLES_SHIFT 4 -#define IOSF_BAR_SHIFT 1 -#define IOSF_SB_BUSY (1 << 0) -#define IOSF_PORT_BUNIT 0x03 -#define IOSF_PORT_PUNIT 0x04 -#define IOSF_PORT_NC 0x11 -#define IOSF_PORT_DPIO 0x12 -#define IOSF_PORT_GPIO_NC0x13 -#define IOSF_PORT_CCK0x14 -#define IOSF_PORT_DPIO_2 0x1a -#define IOSF_PORT_FLISDSI0x1b -#define IOSF_PORT_GPIO_SC0x48 -#define IOSF_PORT_GPIO_SUS 0xa8 -#define IOSF_PORT_CCU0xa9 -#define CHV_IOSF_PORT_GPIO_N 0x13 -#define CHV_IOSF_PORT_GPIO_SE0x48 -#define CHV_IOSF_PORT_GPIO_E 0xa8 -#define CHV_IOSF_PORT_GPIO_SW0xb2 -#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) -#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) - -/* DPIO registers */ -#define DPIO_DEVFN 0 - #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ #define DPIO_SFR_BYPASS (1 << 1) #define DPIO_CMNRST (1 << 0) -/* - * Per pipe/PLL DPIO regs - */ -#define _VLV_PLL_DW3_CH0 0x800c -#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ -#define DPIO_POST_DIV_DAC0 -#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ -#define DPIO_POST_DIV_LVDS1 2 -#define DPIO_POST_DIV_LVDS2 3 -#define DPIO_K_SHIFT (24) /* 4 bits */ -#define DPIO_P1_SHIFT(21) /* 3 bits */ -#define DPIO_P2_SHIFT(16) /* 5 bits */ -#define DPIO_N_SHIFT (12) /* 4 bits */ -#define DPIO_ENABLE_CALIBRATION (1 << 11) -#define DPIO_M1DIV_SHIFT (8) /* 3 bits */ -#define DPIO_M2DIV_MASK 0xff -#define _VLV_PLL_DW3_CH1 0x802c -#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) - -#define _VLV_PLL_DW5_CH0 0x8014 -#define DPIO_REFSEL_OVERRIDE 27 -#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ -#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ -#define DPIO_PLL_REFCLK_SEL_SHIFT16 /* 2 bits */ -#define DPIO_PLL_REFCLK_SEL_MASK 3 -#define DPIO_DRIVER_CTL_SHIFT12 /* always set to 0x8 */ -#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ -#define _VLV_PLL_DW5_CH1 0x8034 -#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) - -#define _VLV_PLL_DW7_CH0 0x801c -#define _VLV_PLL_DW7_CH1 0x803c -#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) - -#define _VLV_PLL_DW8_CH0 0x8040 -#define _VLV_PLL_DW8_CH1 0x8060 -#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) - -#define VLV_PLL_DW9_BCAST 0xc044 -#define _VLV_PLL_DW9_CH0 0x8044 -#define _VLV_PLL_DW9_CH1 0x8064 -#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) - -#define _VLV_PLL_DW10_CH0 0x8048 -#define _VLV_PLL_DW10_CH1 0x8068 -#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) - -#define _VLV_PLL_DW11_CH0 0x804c -#define _VLV_PLL_DW11_CH1 0x806c -#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) - -/* Spec for ref block start counts at DW10 */ -#define VLV_REF_DW13 0x80ac - -#define VLV_CMN_DW00x8100 - -/* - * Per DDI channel DPIO regs - */ - -#define _VLV_PCS_DW0_CH0
