On Wed, Oct 21, 2020 at 01:20:33AM -0700, Lucas De Marchi wrote:
> Just like for rkl and tgl, this should be permanent as well for dg1
> instead just for A0. The commit making it permanent for those platforms
> ended up "racing" with the commit adding the DG1 WAs, so now fix that up.
>
> Cc: Swathi Dhanavanthri
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index fed9503a7c4e..8d24ea769fe6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1768,6 +1768,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
>*/
> wa_write_or(wal, GEN7_FF_THREAD_MODE,
> GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
> +
> + /*
> + * Wa_1606700617
Not sure if you meant to drop the ":tgl" suffix here when you moved it?
This alternate number also shows up in the DG1 database now (but not
RKL) so we could make this "tgl,dg1" to match the spec.
Either way,
Reviewed-by: Matt Roper
> + * Wa_22010271021:tgl,rkl,dg1
> + */
> + wa_masked_en(wal,
> + GEN9_CS_DEBUG_MODE1,
> + FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> @@ -1796,14 +1804,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
>GEN6_RC_SLEEP_PSMI_CONTROL,
>GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
>GEN8_RC_SEMA_IDLE_MSG_DISABLE);
> -
> - /*
> - * Wa_1606700617:tgl
> - * Wa_22010271021:tgl,rkl
> - */
> - wa_masked_en(wal,
> - GEN9_CS_DEBUG_MODE1,
> - FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> if (IS_GEN(i915, 12)) {
> --
> 2.28.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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