Re: [Intel-gfx] [PATCH 5/8] drm/i915/gt: Fix perf limit reasons bit positions
On Thu, 08 Sep 2022 05:37:08 -0700, Sundaresan, Sujaritha wrote:
>
> On 9/8/2022 4:12 PM, Andi Shyti wrote:
> > Hi,
> >
> > On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote:
> >> Perf limit reasons bit positions were off by one.
> >>
> >> Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency
> >> interfaces")
> >> Cc: sta...@vger.kernel.org # v5.18+
> >> Cc: Sujaritha Sundaresan
> >> Cc: Andi Shyti
> >> Signed-off-by: Ashutosh Dixit
> > Thanks Ashutosh!
> >
> >> ---
> >> drivers/gpu/drm/i915/i915_reg.h | 16
> >> 1 file changed, 8 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h
> >> index c413eec3373f..24009786f88b 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -1794,14 +1794,14 @@
> >> #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
> >> #define GT0_PERF_LIMIT_REASONS_MASK0xde3
> >> -#define PROCHOT_MASKREG_BIT(1)
> >> -#define THERMAL_LIMIT_MASK REG_BIT(2)
> >> -#define RATL_MASK REG_BIT(6)
> >> -#define VR_THERMALERT_MASK REG_BIT(7)
> >> -#define VR_TDC_MASK REG_BIT(8)
> >> -#define POWER_LIMIT_4_MASK REG_BIT(9)
> >> -#define POWER_LIMIT_1_MASK REG_BIT(11)
> >> -#define POWER_LIMIT_2_MASK REG_BIT(12)
> >> +#define PROCHOT_MASKREG_BIT(0)
> >> +#define THERMAL_LIMIT_MASK REG_BIT(1)
> >> +#define RATL_MASK REG_BIT(5)
> >> +#define VR_THERMALERT_MASK REG_BIT(6)
> >> +#define VR_TDC_MASK REG_BIT(7)
> >> +#define POWER_LIMIT_4_MASK REG_BIT(8)
> >> +#define POWER_LIMIT_1_MASK REG_BIT(10)
> >> +#define POWER_LIMIT_2_MASK REG_BIT(11)
> > Sujaritha, could you please check and r-b this one?
> >
> > Thanks,
> > Andi
>
> Looks good. I've checked the reg bits.
>
> Reviewed-by : Sujaritha Sundaresan
^
I will fix it so no need to resend but just FYI Patchwork doesn't like the
extra space above so doesn't register the R-b...
Re: [Intel-gfx] [PATCH 5/8] drm/i915/gt: Fix perf limit reasons bit positions
On Thu, Sep 08, 2022 at 06:07:08PM +0530, Sundaresan, Sujaritha wrote:
>
> On 9/8/2022 4:12 PM, Andi Shyti wrote:
> > Hi,
> >
> > On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote:
> > > Perf limit reasons bit positions were off by one.
> > >
> > > Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency
> > > interfaces")
> > > Cc: sta...@vger.kernel.org # v5.18+
> > > Cc: Sujaritha Sundaresan
> > > Cc: Andi Shyti
> > > Signed-off-by: Ashutosh Dixit
> > Thanks Ashutosh!
> >
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 16
> > > 1 file changed, 8 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index c413eec3373f..24009786f88b 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1794,14 +1794,14 @@
> > > #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
> > > #define GT0_PERF_LIMIT_REASONS_MASK 0xde3
> > > -#define PROCHOT_MASK REG_BIT(1)
> > > -#define THERMAL_LIMIT_MASK REG_BIT(2)
> > > -#define RATL_MASK REG_BIT(6)
> > > -#define VR_THERMALERT_MASK REG_BIT(7)
> > > -#define VR_TDC_MASKREG_BIT(8)
> > > -#define POWER_LIMIT_4_MASK REG_BIT(9)
> > > -#define POWER_LIMIT_1_MASK REG_BIT(11)
> > > -#define POWER_LIMIT_2_MASK REG_BIT(12)
> > > +#define PROCHOT_MASK REG_BIT(0)
> > > +#define THERMAL_LIMIT_MASK REG_BIT(1)
> > > +#define RATL_MASK REG_BIT(5)
> > > +#define VR_THERMALERT_MASK REG_BIT(6)
> > > +#define VR_TDC_MASKREG_BIT(7)
> > > +#define POWER_LIMIT_4_MASK REG_BIT(8)
> > > +#define POWER_LIMIT_1_MASK REG_BIT(10)
> > > +#define POWER_LIMIT_2_MASK REG_BIT(11)
> > Sujaritha, could you please check and r-b this one?
> >
> > Thanks,
> > Andi
>
> Looks good. I've checked the reg bits.
>
> Reviewed-by : Sujaritha Sundaresan
Thanks! then:
Acked-by: Andi Shyti
Andi
Re: [Intel-gfx] [PATCH 5/8] drm/i915/gt: Fix perf limit reasons bit positions
On 9/8/2022 4:12 PM, Andi Shyti wrote:
Hi,
On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote:
Perf limit reasons bit positions were off by one.
Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Cc: sta...@vger.kernel.org # v5.18+
Cc: Sujaritha Sundaresan
Cc: Andi Shyti
Signed-off-by: Ashutosh Dixit
Thanks Ashutosh!
---
drivers/gpu/drm/i915/i915_reg.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c413eec3373f..24009786f88b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,14 +1794,14 @@
#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
-#define PROCHOT_MASK REG_BIT(1)
-#define THERMAL_LIMIT_MASK REG_BIT(2)
-#define RATL_MASKREG_BIT(6)
-#define VR_THERMALERT_MASK REG_BIT(7)
-#define VR_TDC_MASK REG_BIT(8)
-#define POWER_LIMIT_4_MASK REG_BIT(9)
-#define POWER_LIMIT_1_MASK REG_BIT(11)
-#define POWER_LIMIT_2_MASK REG_BIT(12)
+#define PROCHOT_MASK REG_BIT(0)
+#define THERMAL_LIMIT_MASK REG_BIT(1)
+#define RATL_MASKREG_BIT(5)
+#define VR_THERMALERT_MASK REG_BIT(6)
+#define VR_TDC_MASK REG_BIT(7)
+#define POWER_LIMIT_4_MASK REG_BIT(8)
+#define POWER_LIMIT_1_MASK REG_BIT(10)
+#define POWER_LIMIT_2_MASK REG_BIT(11)
Sujaritha, could you please check and r-b this one?
Thanks,
Andi
Looks good. I've checked the reg bits.
Reviewed-by : Sujaritha Sundaresan
Re: [Intel-gfx] [PATCH 5/8] drm/i915/gt: Fix perf limit reasons bit positions
Hi,
On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote:
> Perf limit reasons bit positions were off by one.
>
> Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
> Cc: sta...@vger.kernel.org # v5.18+
> Cc: Sujaritha Sundaresan
> Cc: Andi Shyti
> Signed-off-by: Ashutosh Dixit
Thanks Ashutosh!
> ---
> drivers/gpu/drm/i915/i915_reg.h | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c413eec3373f..24009786f88b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1794,14 +1794,14 @@
>
> #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
> #define GT0_PERF_LIMIT_REASONS_MASK0xde3
> -#define PROCHOT_MASK REG_BIT(1)
> -#define THERMAL_LIMIT_MASK REG_BIT(2)
> -#define RATL_MASK REG_BIT(6)
> -#define VR_THERMALERT_MASK REG_BIT(7)
> -#define VR_TDC_MASKREG_BIT(8)
> -#define POWER_LIMIT_4_MASK REG_BIT(9)
> -#define POWER_LIMIT_1_MASK REG_BIT(11)
> -#define POWER_LIMIT_2_MASK REG_BIT(12)
> +#define PROCHOT_MASK REG_BIT(0)
> +#define THERMAL_LIMIT_MASK REG_BIT(1)
> +#define RATL_MASK REG_BIT(5)
> +#define VR_THERMALERT_MASK REG_BIT(6)
> +#define VR_TDC_MASKREG_BIT(7)
> +#define POWER_LIMIT_4_MASK REG_BIT(8)
> +#define POWER_LIMIT_1_MASK REG_BIT(10)
> +#define POWER_LIMIT_2_MASK REG_BIT(11)
Sujaritha, could you please check and r-b this one?
Thanks,
Andi
[Intel-gfx] [PATCH 5/8] drm/i915/gt: Fix perf limit reasons bit positions
Perf limit reasons bit positions were off by one.
Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Cc: sta...@vger.kernel.org # v5.18+
Cc: Sujaritha Sundaresan
Cc: Andi Shyti
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_reg.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c413eec3373f..24009786f88b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,14 +1794,14 @@
#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
-#define PROCHOT_MASK REG_BIT(1)
-#define THERMAL_LIMIT_MASK REG_BIT(2)
-#define RATL_MASKREG_BIT(6)
-#define VR_THERMALERT_MASK REG_BIT(7)
-#define VR_TDC_MASK REG_BIT(8)
-#define POWER_LIMIT_4_MASK REG_BIT(9)
-#define POWER_LIMIT_1_MASK REG_BIT(11)
-#define POWER_LIMIT_2_MASK REG_BIT(12)
+#define PROCHOT_MASK REG_BIT(0)
+#define THERMAL_LIMIT_MASK REG_BIT(1)
+#define RATL_MASKREG_BIT(5)
+#define VR_THERMALERT_MASK REG_BIT(6)
+#define VR_TDC_MASK REG_BIT(7)
+#define POWER_LIMIT_4_MASK REG_BIT(8)
+#define POWER_LIMIT_1_MASK REG_BIT(10)
+#define POWER_LIMIT_2_MASK REG_BIT(11)
#define CHV_CLK_CTL1 _MMIO(0x101100)
#define VLV_CLK_CTL2 _MMIO(0x101104)
--
2.34.1
