Re: [Intel-gfx] [PATCH 5/9] drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines
On Fri, 12 Nov 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT & co. for PCH_TRANSCONF/TRANS_DP_CTL bits, and
> adjust the naming a some bits to be more consistent.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> .../gpu/drm/i915/display/intel_pch_display.c | 13 +++--
> drivers/gpu/drm/i915/i915_reg.h | 58 +--
> 2 files changed, 33 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 81ab761251ae..155c2d19a6bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -166,11 +166,11 @@ static void ilk_enable_pch_transcoder(const struct
> intel_crtc_state *crtc_state)
> if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) ==
> PIPECONF_INTERLACE_IF_ID_ILK) {
> if (HAS_PCH_IBX(dev_priv) &&
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> - val |= TRANS_LEGACY_INTERLACED_ILK;
> + val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
> else
> - val |= TRANS_INTERLACED;
> + val |= TRANS_INTERLACE_INTERLACED;
> } else {
> - val |= TRANS_PROGRESSIVE;
> + val |= TRANS_INTERLACE_PROGRESSIVE;
> }
>
> intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
> @@ -279,7 +279,8 @@ void ilk_pch_enable(struct intel_atomic_state *state,
>
> temp = intel_de_read(dev_priv, reg);
> temp &= ~(TRANS_DP_PORT_SEL_MASK |
> - TRANS_DP_SYNC_MASK |
> + TRANS_DP_VSYNC_ACTIVE_HIGH |
> + TRANS_DP_HSYNC_ACTIVE_HIGH |
> TRANS_DP_BPC_MASK);
> temp |= TRANS_DP_OUTPUT_ENABLE;
> temp |= bpc << 9; /* same format but at 11:9 */
> @@ -423,9 +424,9 @@ static void lpt_enable_pch_transcoder(struct
> drm_i915_private *dev_priv,
> pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
>
> if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
> PIPECONF_INTERLACE_IF_ID_ILK)
> - val |= TRANS_INTERLACED;
> + val |= TRANS_INTERLACE_INTERLACED;
> else
> - val |= TRANS_PROGRESSIVE;
> + val |= TRANS_INTERLACE_PROGRESSIVE;
>
> intel_de_write(dev_priv, LPT_TRANSCONF, val);
> if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d2d5b2fa2a4a..eea009e76e15 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8994,22 +8994,19 @@ enum {
> #define _PCH_TRANSBCONF 0xf1008
> #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF,
> _PCH_TRANSBCONF)
> #define LPT_TRANSCONFPCH_TRANSCONF(PIPE_A) /* lpt has only
> one transcoder */
> -#define TRANS_DISABLE (0 << 31)
> -#define TRANS_ENABLE (1 << 31)
> -#define TRANS_STATE_MASK (1 << 30)
> -#define TRANS_STATE_DISABLE(0 << 30)
> -#define TRANS_STATE_ENABLE (1 << 30)
> -#define TRANS_FRAME_START_DELAY_MASK(3 << 27) /* ibx */
> -#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
> -#define TRANS_INTERLACE_MASK (7 << 21)
> -#define TRANS_PROGRESSIVE (0 << 21)
> -#define TRANS_INTERLACED (3 << 21)
> -#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
> -#define TRANS_8BPC (0 << 5)
> -#define TRANS_10BPC(1 << 5)
> -#define TRANS_6BPC (2 << 5)
> -#define TRANS_12BPC(3 << 5)
> -
> +#define TRANS_ENABLEREG_BIT(31)
> +#define TRANS_STATE_ENABLE REG_BIT(30)
> +#define TRANS_FRAME_START_DELAY_MASKREG_GENMASK(28, 27) /* ibx */
> +#define TRANS_FRAME_START_DELAY(x)
> REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
> +#define TRANS_INTERLACE_MASKREG_GENMASK(23, 21)
> +#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
> +#define TRANS_INTERLACE_LEGACY_VSYNC_IBX
> REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
> +#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
> +#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
> +#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
> +#define TRANS_BPC_10REG_FIELD_PREP(TRANS_BPC_MASK,
> 1)
> +#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
> +#define TRANS_BPC_12REG_FIELD_PREP(TRANS_BPC_MASK,
> 3)
> #define _TRANSA_CHICKEN1 0xf0060
> #define _TRANSB_CHICKEN1 0xf1060
> #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1,
> _TRANSB_CHICKEN1)
> @@ -9219,22 +9216,19 @@ enum {
> #define
[Intel-gfx] [PATCH 5/9] drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines
From: Ville Syrjälä
Use REG_BIT & co. for PCH_TRANSCONF/TRANS_DP_CTL bits, and
adjust the naming a some bits to be more consistent.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_pch_display.c | 13 +++--
drivers/gpu/drm/i915/i915_reg.h | 58 +--
2 files changed, 33 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 81ab761251ae..155c2d19a6bb 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -166,11 +166,11 @@ static void ilk_enable_pch_transcoder(const struct
intel_crtc_state *crtc_state)
if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) ==
PIPECONF_INTERLACE_IF_ID_ILK) {
if (HAS_PCH_IBX(dev_priv) &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
- val |= TRANS_LEGACY_INTERLACED_ILK;
+ val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
else
- val |= TRANS_INTERLACED;
+ val |= TRANS_INTERLACE_INTERLACED;
} else {
- val |= TRANS_PROGRESSIVE;
+ val |= TRANS_INTERLACE_PROGRESSIVE;
}
intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
@@ -279,7 +279,8 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp = intel_de_read(dev_priv, reg);
temp &= ~(TRANS_DP_PORT_SEL_MASK |
- TRANS_DP_SYNC_MASK |
+ TRANS_DP_VSYNC_ACTIVE_HIGH |
+ TRANS_DP_HSYNC_ACTIVE_HIGH |
TRANS_DP_BPC_MASK);
temp |= TRANS_DP_OUTPUT_ENABLE;
temp |= bpc << 9; /* same format but at 11:9 */
@@ -423,9 +424,9 @@ static void lpt_enable_pch_transcoder(struct
drm_i915_private *dev_priv,
pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
PIPECONF_INTERLACE_IF_ID_ILK)
- val |= TRANS_INTERLACED;
+ val |= TRANS_INTERLACE_INTERLACED;
else
- val |= TRANS_PROGRESSIVE;
+ val |= TRANS_INTERLACE_PROGRESSIVE;
intel_de_write(dev_priv, LPT_TRANSCONF, val);
if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d2d5b2fa2a4a..eea009e76e15 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8994,22 +8994,19 @@ enum {
#define _PCH_TRANSBCONF 0xf1008
#define PCH_TRANSCONF(pipe)_MMIO_PIPE(pipe, _PCH_TRANSACONF,
_PCH_TRANSBCONF)
#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one
transcoder */
-#define TRANS_DISABLE (0 << 31)
-#define TRANS_ENABLE (1 << 31)
-#define TRANS_STATE_MASK (1 << 30)
-#define TRANS_STATE_DISABLE(0 << 30)
-#define TRANS_STATE_ENABLE (1 << 30)
-#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
-#define TRANS_FRAME_START_DELAY(x)((x) << 27) /* ibx: 0-3 */
-#define TRANS_INTERLACE_MASK (7 << 21)
-#define TRANS_PROGRESSIVE (0 << 21)
-#define TRANS_INTERLACED (3 << 21)
-#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
-#define TRANS_8BPC (0 << 5)
-#define TRANS_10BPC(1 << 5)
-#define TRANS_6BPC (2 << 5)
-#define TRANS_12BPC(3 << 5)
-
+#define TRANS_ENABLE REG_BIT(31)
+#define TRANS_STATE_ENABLEREG_BIT(30)
+#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
+#define TRANS_FRAME_START_DELAY(x)
REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
+#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
+#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
+#define TRANS_INTERLACE_LEGACY_VSYNC_IBX
REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
+#define TRANS_INTERLACE_INTERLACEDREG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
+#define TRANS_BPC_MASKREG_GENMASK(7, 5) /* ibx */
+#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
+#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
+#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
+#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
#define _TRANSA_CHICKEN10xf0060
#define _TRANSB_CHICKEN10xf1060
#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1,
_TRANSB_CHICKEN1)
@@ -9219,22 +9216,19 @@ enum {
#define _TRANS_DP_CTL_B0xe1300
#define _TRANS_DP_CTL_C0xe2300
#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A,
_TRANS_DP_CTL_B)
-#define TRANS_DP_OUTPUT_ENABLE(1 << 31)
-#define
