Re: [Intel-gfx] [PATCH 5/9] drm/i915: Use enum plane_id in SKL plane code

2016-11-17 Thread Paulo Zanoni
Em Ter, 2016-11-08 às 16:47 +0200, ville.syrj...@linux.intel.com
escreveu:
> From: Ville Syrjälä 
> 
> Replace the intel_plane->plane and hardcoded 0 usage in the SKL plane
> code with intel_plane->id.
> 
> This should make the SKL "primary" and "sprite" code virtually
> identical, so the next logical step would likely be dropping one
> of the copies.

Something something 80 columns something something. Also, this will
need a rebase, but the idea is sane, so with a bug-free rebase:

Reviewed-by: Paulo Zanoni .

> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 34 
>  drivers/gpu/drm/i915/intel_sprite.c  | 50 ++--
> 
>  2 files changed, 43 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e3ed5d1fcf0d..95644c8cc568 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3384,9 +3384,10 @@ static void
> skylake_update_primary_plane(struct drm_plane *plane,
>   struct drm_i915_private *dev_priv = to_i915(dev);
>   struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> >base.crtc);
>   struct drm_framebuffer *fb = plane_state->base.fb;
> + enum plane_id plane_id = to_intel_plane(plane)->id;
>   const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
>   const struct skl_plane_wm *p_wm =
> - &crtc_state->wm.skl.optimal.planes[0];
> + &crtc_state->wm.skl.optimal.planes[plane_id];
>   int pipe = intel_crtc->pipe;
>   u32 plane_ctl;
>   unsigned int rotation = plane_state->base.rotation;
> @@ -3423,32 +3424,32 @@ static void
> skylake_update_primary_plane(struct drm_plane *plane,
>   intel_crtc->adjusted_y = src_y;
>  
>   if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
> - skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
> + skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb,
> plane_id);
>  
> - I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
> - I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
> - I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
> - I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
> + I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
> + I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) |
> src_x);
> + I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
> + I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) |
> src_w);
>  
>   if (scaler_id >= 0) {
>   uint32_t ps_ctrl = 0;
>  
>   WARN_ON(!dst_w || !dst_h);
> - ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
> + ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
>   crtc_state-
> >scaler_state.scalers[scaler_id].mode;
>   I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
>   I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
>   I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x
> << 16) | dst_y);
>   I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w <<
> 16) | dst_h);
> - I915_WRITE(PLANE_POS(pipe, 0), 0);
> + I915_WRITE(PLANE_POS(pipe, plane_id), 0);
>   } else {
> - I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) |
> dst_x);
> + I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16)
> | dst_x);
>   }
>  
> - I915_WRITE(PLANE_SURF(pipe, 0),
> + I915_WRITE(PLANE_SURF(pipe, plane_id),
>      intel_fb_gtt_offset(fb, rotation) + surf_addr);
>  
> - POSTING_READ(PLANE_SURF(pipe, 0));
> + POSTING_READ(PLANE_SURF(pipe, plane_id));
>  }
>  
>  static void skylake_disable_primary_plane(struct drm_plane *primary,
> @@ -3458,7 +3459,8 @@ static void
> skylake_disable_primary_plane(struct drm_plane *primary,
>   struct drm_i915_private *dev_priv = to_i915(dev);
>   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>   struct intel_crtc_state *cstate = to_intel_crtc_state(crtc-
> >state);
> - const struct skl_plane_wm *p_wm = &cstate-
> >wm.skl.optimal.planes[0];
> + enum plane_id plane_id = to_intel_plane(primary)->id;
> + const struct skl_plane_wm *p_wm = &cstate-
> >wm.skl.optimal.planes[plane_id];
>   int pipe = intel_crtc->pipe;
>  
>   /*
> @@ -3467,11 +3469,11 @@ static void
> skylake_disable_primary_plane(struct drm_plane *primary,
>    */
>   if (!crtc->primary->state->visible)
>   skl_write_plane_wm(intel_crtc, p_wm,
> -    &dev_priv->wm.skl_results.ddb,
> 0);
> +    &dev_priv->wm.skl_results.ddb,
> plane_id);
>  
> - I915_WRITE(PLANE_CTL(pipe, 0), 0);
> - I915_WRITE(PLANE_SURF(pipe, 0), 0);
> - POSTING_READ(PLANE_SURF(pipe, 0));
> + I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
> + I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
> + POSTING_READ(PLANE_SURF(pipe, plane_id

[Intel-gfx] [PATCH 5/9] drm/i915: Use enum plane_id in SKL plane code

2016-11-08 Thread ville . syrjala
From: Ville Syrjälä 

Replace the intel_plane->plane and hardcoded 0 usage in the SKL plane
code with intel_plane->id.

This should make the SKL "primary" and "sprite" code virtually
identical, so the next logical step would likely be dropping one
of the copies.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 34 
 drivers/gpu/drm/i915/intel_sprite.c  | 50 ++--
 2 files changed, 43 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e3ed5d1fcf0d..95644c8cc568 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3384,9 +3384,10 @@ static void skylake_update_primary_plane(struct 
drm_plane *plane,
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_framebuffer *fb = plane_state->base.fb;
+   enum plane_id plane_id = to_intel_plane(plane)->id;
const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
const struct skl_plane_wm *p_wm =
-   &crtc_state->wm.skl.optimal.planes[0];
+   &crtc_state->wm.skl.optimal.planes[plane_id];
int pipe = intel_crtc->pipe;
u32 plane_ctl;
unsigned int rotation = plane_state->base.rotation;
@@ -3423,32 +3424,32 @@ static void skylake_update_primary_plane(struct 
drm_plane *plane,
intel_crtc->adjusted_y = src_y;
 
if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
-   skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
+   skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, plane_id);
 
-   I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
-   I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
-   I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
-   I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
+   I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
+   I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
+   I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
+   I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 
if (scaler_id >= 0) {
uint32_t ps_ctrl = 0;
 
WARN_ON(!dst_w || !dst_h);
-   ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
+   ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
crtc_state->scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | 
dst_y);
I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | 
dst_h);
-   I915_WRITE(PLANE_POS(pipe, 0), 0);
+   I915_WRITE(PLANE_POS(pipe, plane_id), 0);
} else {
-   I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
+   I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
}
 
-   I915_WRITE(PLANE_SURF(pipe, 0),
+   I915_WRITE(PLANE_SURF(pipe, plane_id),
   intel_fb_gtt_offset(fb, rotation) + surf_addr);
 
-   POSTING_READ(PLANE_SURF(pipe, 0));
+   POSTING_READ(PLANE_SURF(pipe, plane_id));
 }
 
 static void skylake_disable_primary_plane(struct drm_plane *primary,
@@ -3458,7 +3459,8 @@ static void skylake_disable_primary_plane(struct 
drm_plane *primary,
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
-   const struct skl_plane_wm *p_wm = &cstate->wm.skl.optimal.planes[0];
+   enum plane_id plane_id = to_intel_plane(primary)->id;
+   const struct skl_plane_wm *p_wm = 
&cstate->wm.skl.optimal.planes[plane_id];
int pipe = intel_crtc->pipe;
 
/*
@@ -3467,11 +3469,11 @@ static void skylake_disable_primary_plane(struct 
drm_plane *primary,
 */
if (!crtc->primary->state->visible)
skl_write_plane_wm(intel_crtc, p_wm,
-  &dev_priv->wm.skl_results.ddb, 0);
+  &dev_priv->wm.skl_results.ddb, plane_id);
 
-   I915_WRITE(PLANE_CTL(pipe, 0), 0);
-   I915_WRITE(PLANE_SURF(pipe, 0), 0);
-   POSTING_READ(PLANE_SURF(pipe, 0));
+   I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
+   I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
+   POSTING_READ(PLANE_SURF(pipe, plane_id));
 }
 
 /* Assume fb object is pinned & idle & fenced and just update base pointers */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 4b44863a07c2..91d47d19f4a9 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -203,13 +203,13 @@ skl_update_plane(stru