[Intel-gfx] [PATCH 6/7] drm/i915/skl: Query display address through a wrapper
From: Tvrtko Ursulin
Need to do this in order to support 90/270 rotated display.
v2: Pass in drm_plane instead of plane index to intel_obj_display_address.
v3:
* Renamed intel_obj_display_address to intel_plane_obj_offset.
(Chris Wilson)
* Simplified rotation check to bitwise AND. (Chris Wilson)
v4:
* Extracted 90/270 rotation check into a helper function. (Michel Thierry)
v5:
* Rebased for ggtt view changes.
For: VIZ-4545
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel Thierry
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_display.c | 23 +--
drivers/gpu/drm/i915/intel_drv.h | 9 +
drivers/gpu/drm/i915/intel_sprite.c | 5 -
3 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f605b09..d1f9099 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2301,8 +2301,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
struct drm_framebuffer *fb,
if (!plane_state)
return 0;
- if (!(plane_state->rotation &
- (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270
+ if (!intel_rotation_90_or_270(plane_state->rotation))
return 0;
*view = rotated_view;
@@ -2900,6 +2899,17 @@ u32 intel_fb_stride_alignment(struct drm_device *dev,
uint64_t fb_modifier,
}
}
+unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
+struct drm_i915_gem_object *obj)
+{
+ enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
+
+ if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
+ view = I915_GGTT_VIEW_ROTATED;
+
+ return i915_gem_obj_ggtt_offset_view(obj, view);
+}
+
static void skylake_update_primary_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int x, int y)
@@ -2910,6 +2920,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
struct drm_i915_gem_object *obj;
int pipe = intel_crtc->pipe;
u32 plane_ctl, stride_div;
+ unsigned long surf_addr;
if (!intel_crtc->primary_enabled) {
I915_WRITE(PLANE_CTL(pipe, 0), 0);
@@ -2976,16 +2987,16 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
obj = intel_fb_obj(fb);
stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
fb->pixel_format);
+ surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
-
I915_WRITE(PLANE_POS(pipe, 0), 0);
I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
I915_WRITE(PLANE_SIZE(pipe, 0),
(intel_crtc->config->pipe_src_h - 1) << 16 |
(intel_crtc->config->pipe_src_w - 1));
I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
- I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
+ I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
POSTING_READ(PLANE_SURF(pipe, 0));
}
@@ -10079,8 +10090,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (ret)
goto cleanup_pending;
- work->gtt_offset =
- i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
+ work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
+ + intel_crtc->dspaddr_offset;
if (use_mmio_flip(ring, obj)) {
ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cb00bd0..db0e7bf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -988,6 +988,12 @@ unsigned int
intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
uint64_t fb_format_modifier);
+static inline bool
+intel_rotation_90_or_270(unsigned int rotation)
+{
+ return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
+}
+
/* shared dpll functions */
struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
void assert_shared_dpll(struct drm_i915_private *dev_priv,
@@ -1042,6 +1048,9 @@ void intel_mode_from_pipe_config(struct drm_display_mode
*mode,
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
+unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
+struct drm_i915_gem_object *obj);
+
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
diff --git a/driv
Re: [Intel-gfx] [PATCH 6/7] drm/i915/skl: Query display address through a wrapper
On ti, 2015-03-17 at 15:45 +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Need to do this in order to support 90/270 rotated display.
>
> v2: Pass in drm_plane instead of plane index to intel_obj_display_address.
>
> v3:
> * Renamed intel_obj_display_address to intel_plane_obj_offset.
> (Chris Wilson)
> * Simplified rotation check to bitwise AND. (Chris Wilson)
>
> v4:
> * Extracted 90/270 rotation check into a helper function. (Michel Thierry)
>
> v5:
> * Rebased for ggtt view changes.
>
> For: VIZ-4545
> Signed-off-by: Tvrtko Ursulin
> Reviewed-by: Michel Thierry
Reviewed-by: Joonas Lahtinen (v5)
> ---
> drivers/gpu/drm/i915/intel_display.c | 23 +--
> drivers/gpu/drm/i915/intel_drv.h | 9 +
> drivers/gpu/drm/i915/intel_sprite.c | 5 -
> 3 files changed, 30 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c2c3a76..9af73b1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2263,8 +2263,7 @@ int intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
> if (!plane_state)
> return 0;
>
> - if (!(plane_state->rotation &
> - (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270
> + if (!intel_rotation_90_or_270(plane_state->rotation))
> return 0;
>
> *view = rotated_view;
> @@ -2862,6 +2861,17 @@ u32 intel_fb_stride_alignment(struct drm_device *dev,
> uint64_t fb_modifier,
> }
> }
>
> +unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
> + struct drm_i915_gem_object *obj)
> +{
> + enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
> +
> + if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
> + view = I915_GGTT_VIEW_ROTATED;
> +
> + return i915_gem_obj_ggtt_offset_view(obj, view);
> +}
> +
> static void skylake_update_primary_plane(struct drm_crtc *crtc,
>struct drm_framebuffer *fb,
>int x, int y)
> @@ -2872,6 +2882,7 @@ static void skylake_update_primary_plane(struct
> drm_crtc *crtc,
> struct drm_i915_gem_object *obj;
> int pipe = intel_crtc->pipe;
> u32 plane_ctl, stride_div;
> + unsigned long surf_addr;
>
> if (!intel_crtc->primary_enabled) {
> I915_WRITE(PLANE_CTL(pipe, 0), 0);
> @@ -2938,16 +2949,16 @@ static void skylake_update_primary_plane(struct
> drm_crtc *crtc,
> obj = intel_fb_obj(fb);
> stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
> fb->pixel_format);
> + surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
>
> I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
> -
> I915_WRITE(PLANE_POS(pipe, 0), 0);
> I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> I915_WRITE(PLANE_SIZE(pipe, 0),
> (intel_crtc->config->pipe_src_h - 1) << 16 |
> (intel_crtc->config->pipe_src_w - 1));
> I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
> - I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
> + I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
>
> POSTING_READ(PLANE_SURF(pipe, 0));
> }
> @@ -10039,8 +10050,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> if (ret)
> goto cleanup_pending;
>
> - work->gtt_offset =
> - i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
> + work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
> + + intel_crtc->dspaddr_offset;
>
> if (use_mmio_flip(ring, obj)) {
> ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 53a1372..ae28fb4 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -991,6 +991,12 @@ unsigned int
> intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
> uint64_t fb_format_modifier);
>
> +static inline bool
> +intel_rotation_90_or_270(unsigned int rotation)
> +{
> + return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
> +}
> +
> /* shared dpll functions */
> struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
> void assert_shared_dpll(struct drm_i915_private *dev_priv,
> @@ -1045,6 +1051,9 @@ void intel_mode_from_pipe_config(struct
> drm_display_mode *mode,
> void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
> void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
>
> +unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
> + struct drm_i915_gem_obje
[Intel-gfx] [PATCH 6/7] drm/i915/skl: Query display address through a wrapper
From: Tvrtko Ursulin
Need to do this in order to support 90/270 rotated display.
v2: Pass in drm_plane instead of plane index to intel_obj_display_address.
v3:
* Renamed intel_obj_display_address to intel_plane_obj_offset.
(Chris Wilson)
* Simplified rotation check to bitwise AND. (Chris Wilson)
v4:
* Extracted 90/270 rotation check into a helper function. (Michel Thierry)
v5:
* Rebased for ggtt view changes.
For: VIZ-4545
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_display.c | 23 +--
drivers/gpu/drm/i915/intel_drv.h | 9 +
drivers/gpu/drm/i915/intel_sprite.c | 5 -
3 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c2c3a76..9af73b1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2263,8 +2263,7 @@ int intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
if (!plane_state)
return 0;
- if (!(plane_state->rotation &
- (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270
+ if (!intel_rotation_90_or_270(plane_state->rotation))
return 0;
*view = rotated_view;
@@ -2862,6 +2861,17 @@ u32 intel_fb_stride_alignment(struct drm_device *dev,
uint64_t fb_modifier,
}
}
+unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
+struct drm_i915_gem_object *obj)
+{
+ enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
+
+ if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
+ view = I915_GGTT_VIEW_ROTATED;
+
+ return i915_gem_obj_ggtt_offset_view(obj, view);
+}
+
static void skylake_update_primary_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int x, int y)
@@ -2872,6 +2882,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
struct drm_i915_gem_object *obj;
int pipe = intel_crtc->pipe;
u32 plane_ctl, stride_div;
+ unsigned long surf_addr;
if (!intel_crtc->primary_enabled) {
I915_WRITE(PLANE_CTL(pipe, 0), 0);
@@ -2938,16 +2949,16 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
obj = intel_fb_obj(fb);
stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
fb->pixel_format);
+ surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
-
I915_WRITE(PLANE_POS(pipe, 0), 0);
I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
I915_WRITE(PLANE_SIZE(pipe, 0),
(intel_crtc->config->pipe_src_h - 1) << 16 |
(intel_crtc->config->pipe_src_w - 1));
I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
- I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
+ I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
POSTING_READ(PLANE_SURF(pipe, 0));
}
@@ -10039,8 +10050,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (ret)
goto cleanup_pending;
- work->gtt_offset =
- i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
+ work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
+ + intel_crtc->dspaddr_offset;
if (use_mmio_flip(ring, obj)) {
ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 53a1372..ae28fb4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -991,6 +991,12 @@ unsigned int
intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
uint64_t fb_format_modifier);
+static inline bool
+intel_rotation_90_or_270(unsigned int rotation)
+{
+ return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
+}
+
/* shared dpll functions */
struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
void assert_shared_dpll(struct drm_i915_private *dev_priv,
@@ -1045,6 +1051,9 @@ void intel_mode_from_pipe_config(struct drm_display_mode
*mode,
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
+unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
+struct drm_i915_gem_object *obj);
+
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915
[Intel-gfx] [PATCH 6/7] drm/i915/skl: Query display address through a wrapper
From: Tvrtko Ursulin
Need to do this in order to support 90/270 rotated display.
v2: Pass in drm_plane instead of plane index to intel_obj_display_address.
v3:
* Renamed intel_obj_display_address to intel_plane_obj_offset.
(Chris Wilson)
* Simplified rotation check to bitwise AND. (Chris Wilson)
v4:
* Extracted 90/270 rotation check into a helper function. (Michel Thierry)
For: VIZ-4545
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 24 ++--
drivers/gpu/drm/i915/intel_drv.h | 9 +
drivers/gpu/drm/i915/intel_sprite.c | 5 -
5 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b04b07d..e12b6f3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2879,6 +2879,13 @@ i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
}
static inline unsigned long
+i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *obj,
+ enum i915_ggtt_view_type view)
+{
+ return i915_gem_obj_offset_view(obj, i915_obj_to_ggtt(obj), view);
+}
+
+static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ecedda5..ba99bfe 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5181,8 +5181,8 @@ unsigned long i915_gem_obj_offset_view(struct
drm_i915_gem_object *o,
return vma->node.start;
}
- WARN(1, "%s vma for this object not found.\n",
-i915_is_ggtt(vm) ? "global" : "ppgtt");
+ WARN(1, "%s vma for this object not found. (view=%u)\n",
+i915_is_ggtt(vm) ? "global" : "ppgtt", view);
return -1;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9867f55..c7ead35 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2258,8 +2258,7 @@ int intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
if (!plane_state)
return 0;
- if (!(plane_state->rotation &
- (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270
+ if (!intel_rotation_90_or_270(plane_state->rotation))
return 0;
*view = rotated_view;
@@ -2864,6 +2863,17 @@ u32 intel_fb_stride_alignment(struct drm_device *dev,
uint64_t fb_modifier,
}
}
+unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
+struct drm_i915_gem_object *obj)
+{
+ enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
+
+ if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
+ view = I915_GGTT_VIEW_ROTATED;
+
+ return i915_gem_obj_ggtt_offset_view(obj, view);
+}
+
static void skylake_update_primary_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int x, int y)
@@ -2874,6 +2884,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
struct drm_i915_gem_object *obj;
int pipe = intel_crtc->pipe;
u32 plane_ctl, stride_div;
+ unsigned long surf_addr;
if (!intel_crtc->primary_enabled) {
I915_WRITE(PLANE_CTL(pipe, 0), 0);
@@ -2940,11 +2951,12 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
obj = intel_fb_obj(fb);
stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
fb->pixel_format);
+ surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
- i915_gem_obj_ggtt_offset(obj),
+ surf_addr,
x, y, fb->width, fb->height,
fb->pitches[0]);
@@ -2954,7 +2966,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
(intel_crtc->config->pipe_src_h - 1) << 16 |
(intel_crtc->config->pipe_src_w - 1));
I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
- I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
+ I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
POSTING_READ(PLANE_SURF(pipe, 0));
}
@@ -9987,8 +,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (ret)
goto cleanup_pending;
- work->gtt_offset =
- i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
+ work->gtt_offset = intel_plane_o
