Re: [Intel-gfx] [PATCH 7/8] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI

[kbuild test robot]

Hi Manasi,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180329]
[cannot apply to v4.16-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Paulo-Zanoni/ICL-PLLs-DP-HDMI-and-misc-display-v2/20180330-131619
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-h0-03311214 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

^
   In file included from include/linux/list.h:9:0,
from include/linux/kobject.h:19,
from include/linux/device.h:16,
from include/linux/i2c.h:30,
from include/drm/drm_scdc_helper.h:27,
from drivers/gpu//drm/i915/intel_ddi.c:28:
   drivers/gpu//drm/i915/intel_ddi.c:784:28: error: 
'icl_combo_phy_ddi_translations_dp_hdmi_1_05V' undeclared (first use in this 
function)
   *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
   ^
   include/linux/kernel.h:71:33: note: in definition of macro 'ARRAY_SIZE'
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + 
__must_be_array(arr))
^
   In file included from include/linux/kernel.h:15:0,
from include/linux/list.h:9,
from include/linux/kobject.h:19,
from include/linux/device.h:16,
from include/linux/i2c.h:30,
from include/drm/drm_scdc_helper.h:27,
from drivers/gpu//drm/i915/intel_ddi.c:28:
   include/linux/build_bug.h:29:45: error: bit-field '' width not an 
integer constant
#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); }))
^
   include/linux/compiler-gcc.h:65:28: note: in expansion of macro 
'BUILD_BUG_ON_ZERO'
#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
   ^
   include/linux/kernel.h:71:59: note: in expansion of macro '__must_be_array'
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + 
__must_be_array(arr))
  ^
   drivers/gpu//drm/i915/intel_ddi.c:784:17: note: in expansion of macro 
'ARRAY_SIZE'
   *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
^
   drivers/gpu//drm/i915/intel_ddi.c: In function 'icl_pll_to_ddi_pll_sel':
   drivers/gpu//drm/i915/intel_ddi.c:939:35: error: 'const struct 
intel_shared_dpll' has no member named 'info'
 const enum intel_dpll_id id = pll->info->id;
  ^
   drivers/gpu//drm/i915/intel_ddi.c: In function 
'icl_ddi_combo_vswing_program':
   drivers/gpu//drm/i915/intel_ddi.c:2142:2: error: implicit declaration of 
function 'ICL_PORT_TX_DW5_LN0' [-Werror=implicit-function-declaration]
 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
 ^
   In file included from drivers/gpu//drm/i915/intel_ddi.c:29:0:
   drivers/gpu//drm/i915/i915_drv.h:3857:25: error: incompatible type for 
argument 2 of 'dev_priv->uncore.funcs.mmio_readl'
#define I915_READ(reg)  dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), 
true)
^
   drivers/gpu//drm/i915/intel_ddi.c:2142:8: note: in expansion of macro 
'I915_READ'
 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
   ^
   drivers/gpu//drm/i915/intel_ddi.c:2142:2: note: expected 'i915_reg_t' but 
argument is of type 'int'
 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
 ^
   drivers/gpu//drm/i915/intel_ddi.c:2145:2: error: implicit declaration of 
function 'ICL_PORT_TX_DW5_GRP' [-Werror=implicit-function-declaration]
 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
 ^
   In file included from drivers/gpu//drm/i915/intel_ddi.c:29:0:
   drivers/gpu//drm/i915/i915_drv.h:3858:30: error: incompatible type for 
argument 2 of 'dev_priv->uncore.funcs.mmio_writel'
#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, 
(reg), (val), true)
 ^
   drivers/gpu//drm/i915/intel_ddi.c:2145:2: note: in expansion of macro 
'I915_WRITE'
 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
 ^
   drivers/gpu//drm/i915/intel_ddi.c:2145:2: note: expected 'i915_reg_t' but 
argument is of type 'int'
   In file included from drivers/gpu//drm/i915/intel_ddi.c:29:0:
   drivers/gpu//drm/i915/i915_drv.h:3857:25: error: incompatible type for 
argument 2 of 'dev_priv->uncore.funcs.mmio_readl'
#define I915_READ(reg)  dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), 
true)
^
   drivers/gpu//drm/i915/intel_ddi.c:2148:8: 

[Intel-gfx] [PATCH 7/8] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI

[Paulo Zanoni]

From: Manasi Navare 

This is an important part of the DDI initalization as well as
for changing the voltage during DisplayPort link training.

The Voltage swing seqeuence is similar to Cannonlake.
However it has different register definitions and hence
it makes sense to create a separate vswing sequence and
program functions for ICL to leave room for more changes
in case the Bspec changes later and deviates from CNL sequence.

v2:
Use ~TAP3_DISABLE for enbaling that bit (Jani Nikula)

v3:
* Use dw4_scaling column for PORT_TX_DW4 values (Rodrigo)

v4:
* Call it combo_vswing, use switch statement (Paulo)

v5 (from Paulo):
* Fix a typo.
* s/rate < 60/rate <= 60/.
* Don't remove blank lines that should be there.

v6:
* Rebased by Rodrigo on top of Cannonlake changes
  where non vswing sequences are not aligned with iboost
  anymore.

v7: Another rebase after an upstream rework.

v8 (from Paulo):
* Adjust the code to the upstream output type changes.
* Squash the patch that moved some functions up.
* Merge both get_combo_buf_trans functions in order to simplify the
  code.
* Change the changelog format.

v9 (from Paulo):
* Use RTERM_SELECT instead of SCALING_MODE_SEL.
* Adjust the output type handling according to how the other platforms
  do it now.

Cc: Jani Nikula 
Cc: James Ausmus 
Signed-off-by: Manasi Navare 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_ddi.c | 191 ++-
 1 file changed, 188 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 10223ffcceab..bfe3e10e080d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -870,6 +870,45 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, 
int *n_entries)
}
 }
 
+static const struct icl_combo_phy_ddi_buf_trans *
+icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
+   int type, int *n_entries)
+{
+   u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
+
+   if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
+   switch (voltage) {
+   case VOLTAGE_INFO_0_85V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
+   return icl_combo_phy_ddi_translations_edp_0_85V;
+   case VOLTAGE_INFO_0_95V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
+   return icl_combo_phy_ddi_translations_edp_0_95V;
+   case VOLTAGE_INFO_1_05V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
+   return icl_combo_phy_ddi_translations_edp_1_05V;
+   default:
+   MISSING_CASE(voltage);
+   return NULL;
+   }
+   } else {
+   switch (voltage) {
+   case VOLTAGE_INFO_0_85V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
+   return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
+   case VOLTAGE_INFO_0_95V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
+   return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
+   case VOLTAGE_INFO_1_05V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
+   return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
+   default:
+   MISSING_CASE(voltage);
+   return NULL;
+   }
+   }
+}
+
 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
port)
 {
int n_entries, level, default_entry;
@@ -2201,6 +2240,146 @@ static void cnl_ddi_vswing_sequence(struct 
intel_encoder *encoder,
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
 }
 
+static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
+u32 level, enum port port, int type)
+{
+   const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
+   u32 n_entries, val;
+   int ln;
+
+   ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
+  _entries);
+   if (!ddi_translations)
+   return;
+
+   if (level >= n_entries) {
+   DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d 
instead.", level, n_entries - 1);
+   level = n_entries - 1;
+   }
+
+   /* Set PORT_TX_DW5 Scaling Mode Sel to 110b. */
+   val =