Re: [Intel-gfx] [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence
On Wed, Nov 12, 2014 at 10:28:10AM +0100, Daniel Vetter wrote: > On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote: > > On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote: > > > From: Mika Kuoppala > > > > > > As per latest pm guide, we need to do this also on > > > past hsw. > > > > Yep, matches the doc. > > > > Reviewed-by: Ville Syrjälä > > Queued for -next, thanks for the patch. > > > > BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't > > see such a thing documented in the HSW PM guide I have here. Maybe we can > > just drop the HSW special case? > > Iirc (commit message is silent unfortunately) this is for the GT3. And > since they're 0 on other hsw we've opted for a tricky silent gt3 enabling > by claiming this is for all of hsw. At least that's the story I remember. > > No idea whether bdw gt3 would need this, too. Might be good to > double-check. The docs claim these are the same old thread wish result bits ever since snb. I just tried intel_reg_read on hsw gt2 and gt3 and both give identical results to ivb. So my hunch is that we can just drop the hsw special case. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence
On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote: > On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote: > > From: Mika Kuoppala > > > > As per latest pm guide, we need to do this also on > > past hsw. > > Yep, matches the doc. > > Reviewed-by: Ville Syrjälä Queued for -next, thanks for the patch. > > BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't > see such a thing documented in the HSW PM guide I have here. Maybe we can > just drop the HSW special case? Iirc (commit message is silent unfortunately) this is for the GT3. And since they're 0 on other hsw we've opted for a tricky silent gt3 enabling by claiming this is for all of hsw. At least that's the story I remember. No idea whether bdw gt3 would need this, too. Might be good to double-check. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence
On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> > From: Mika Kuoppala
> >
> > As per latest pm guide, we need to do this also on
> > past hsw.
>
> Yep, matches the doc.
>
> Reviewed-by: Ville Syrjälä
>
> BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't
> see such a thing documented in the HSW PM guide I have here. Maybe we can
> just drop the HSW special case?
>
> Also I wonder if we want this on CHV too. I should probably know, but I
> dont't. I'll go bash some registers and see what they say...
So the register doesn't seem to exist on CHV. All I get is 0x0, no
matter if the GT is idle or busy. rc6 residency keeps ticking along
at a constant rate so it seems to be in rc6 when I tried this.
# ./intel_reg_read 0x13805c
0x13805C : 0x0
# IGT_NO_FORCEWAKE=1 ./intel_reg_read 0x13805c
0x13805C : 0x0
On IVB it clearly works:
# ./intel_reg_read 0x13805c
0x13805C : 0x4000
# IGT_NO_FORCEWAKE=1 ./intel_reg_read 0x13805c
0x13805C : 0x30303
I think someone needs to try this on VLV too...
>
> >
> > Cc: Ville Syrjälä
> > Cc: Chris Wilson
> > Cc: Damien Lespiau
> > Signed-off-by: Mika Kuoppala
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/intel_uncore.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index 6a0c3fb..86a755a 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -120,8 +120,7 @@ static void __gen7_gt_force_wake_mt_get(struct
> > drm_i915_private *dev_priv,
> > DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
> >
> > /* WaRsForcewakeWaitTC0:ivb,hsw */
> > - if (INTEL_INFO(dev_priv->dev)->gen < 8)
> > - __gen6_gt_wait_for_thread_c0(dev_priv);
> > + __gen6_gt_wait_for_thread_c0(dev_priv);
> > }
> >
> > static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
> > --
> > 1.9.3
>
> --
> Ville Syrjälä
> Intel OTC
> ___
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--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence
On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> From: Mika Kuoppala
>
> As per latest pm guide, we need to do this also on
> past hsw.
Yep, matches the doc.
Reviewed-by: Ville Syrjälä
BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't
see such a thing documented in the HSW PM guide I have here. Maybe we can
just drop the HSW special case?
Also I wonder if we want this on CHV too. I should probably know, but I
dont't. I'll go bash some registers and see what they say...
>
> Cc: Ville Syrjälä
> Cc: Chris Wilson
> Cc: Damien Lespiau
> Signed-off-by: Mika Kuoppala
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 6a0c3fb..86a755a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -120,8 +120,7 @@ static void __gen7_gt_force_wake_mt_get(struct
> drm_i915_private *dev_priv,
> DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
>
> /* WaRsForcewakeWaitTC0:ivb,hsw */
> - if (INTEL_INFO(dev_priv->dev)->gen < 8)
> - __gen6_gt_wait_for_thread_c0(dev_priv);
> + __gen6_gt_wait_for_thread_c0(dev_priv);
> }
>
> static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
> --
> 1.9.3
--
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence
From: Mika Kuoppala
As per latest pm guide, we need to do this also on
past hsw.
Cc: Ville Syrjälä
Cc: Chris Wilson
Cc: Damien Lespiau
Signed-off-by: Mika Kuoppala
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 6a0c3fb..86a755a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -120,8 +120,7 @@ static void __gen7_gt_force_wake_mt_get(struct
drm_i915_private *dev_priv,
DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
/* WaRsForcewakeWaitTC0:ivb,hsw */
- if (INTEL_INFO(dev_priv->dev)->gen < 8)
- __gen6_gt_wait_for_thread_c0(dev_priv);
+ __gen6_gt_wait_for_thread_c0(dev_priv);
}
static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
--
1.9.3
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