Re: [Intel-gfx] [PATCH V5] drm/i915/gt: Add workaround 14016712196

2023-06-05 Thread Andi Shyti 
Hi Tejas,

On Thu, Jun 01, 2023 at 04:39:59PM +0530, Tejas Upadhyay wrote:
> For mtl, workaround suggests that, SW insert a
> dummy PIPE_CONTROL prior to PIPE_CONTROL which
> contains a post sync: Timestamp or Write Immediate.
> 
> Bspec: 72197
> 
> V5:
>   - Remove ret variable - Andi
> V4:
>   - Update commit message, avoid returing cs - Andi/Matt
> V3:
>   - Wrap dummy pipe control stuff in API - Andi
> V2:
>   - Fix  kernel test robot warnings
> 
> Closes: 
> https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/
> Reviewed-by: Andi Shyti 
> Signed-off-by: Tejas Upadhyay 

pushed to drm-intel-gt-next.

Thanks,
Andi

Re: [Intel-gfx] [PATCH V5] drm/i915/gt: Add workaround 14016712196

2023-06-01 Thread Andrzej Hajda 

On 01.06.2023 13:09, Tejas Upadhyay wrote:

For mtl, workaround suggests that, SW insert a
dummy PIPE_CONTROL prior to PIPE_CONTROL which
contains a post sync: Timestamp or Write Immediate.

Bspec: 72197

V5:
   - Remove ret variable - Andi
V4:
   - Update commit message, avoid returing cs - Andi/Matt
V3:
   - Wrap dummy pipe control stuff in API - Andi
V2:
   - Fix  kernel test robot warnings

Closes: 
https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/
Reviewed-by: Andi Shyti 
Signed-off-by: Tejas Upadhyay 


Reviewed-by: Andrzej Hajda 

Regards
Andrzej


---
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38 
  1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..23857cc08eca 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -177,14 +177,40 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 
*cs, const i915_reg_t inv
return cs;
  }
  
+static int mtl_dummy_pipe_control(struct i915_request *rq)

+{
+   /* Wa_14016712196 */
+   if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
+   IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+   u32 *cs;
+
+   /* dummy PIPE_CONTROL + depth flush */
+   cs = intel_ring_begin(rq, 6);
+   if (IS_ERR(cs))
+   return PTR_ERR(cs);
+   cs = gen12_emit_pipe_control(cs,
+0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+LRC_PPHWSP_SCRATCH_ADDR);
+   intel_ring_advance(rq, cs);
+   }
+
+   return 0;
+}
+
  int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
  {
struct intel_engine_cs *engine = rq->engine;
  
  	if (mode & EMIT_FLUSH) {

u32 flags = 0;
+   int err;
u32 *cs;
  
+		err = mtl_dummy_pipe_control(rq);

+   if (err)
+   return err;
+
flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -217,6 +243,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE) {
u32 flags = 0;
u32 *cs, count;
+   int err;
+
+   err = mtl_dummy_pipe_control(rq);
+   if (err)
+   return err;
  
  		flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;

flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -733,6 +764,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request 
*rq, u32 *cs)
 PIPE_CONTROL_DC_FLUSH_ENABLE |
 PIPE_CONTROL_FLUSH_ENABLE);
  
+	/* Wa_14016712196 */

+   if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+   IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+   /* dummy PIPE_CONTROL + depth flush */
+   cs = gen12_emit_pipe_control(cs, 0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
+
if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 
50))
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;

[Intel-gfx] [PATCH V5] drm/i915/gt: Add workaround 14016712196

2023-06-01 Thread Tejas Upadhyay 
For mtl, workaround suggests that, SW insert a
dummy PIPE_CONTROL prior to PIPE_CONTROL which
contains a post sync: Timestamp or Write Immediate.

Bspec: 72197

V5:
  - Remove ret variable - Andi
V4:
  - Update commit message, avoid returing cs - Andi/Matt
V3:
  - Wrap dummy pipe control stuff in API - Andi
V2:
  - Fix  kernel test robot warnings

Closes: 
https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/
Reviewed-by: Andi Shyti 
Signed-off-by: Tejas Upadhyay 
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38 
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..23857cc08eca 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -177,14 +177,40 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 
*cs, const i915_reg_t inv
return cs;
 }
 
+static int mtl_dummy_pipe_control(struct i915_request *rq)
+{
+   /* Wa_14016712196 */
+   if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
+   IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+   u32 *cs;
+
+   /* dummy PIPE_CONTROL + depth flush */
+   cs = intel_ring_begin(rq, 6);
+   if (IS_ERR(cs))
+   return PTR_ERR(cs);
+   cs = gen12_emit_pipe_control(cs,
+0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+LRC_PPHWSP_SCRATCH_ADDR);
+   intel_ring_advance(rq, cs);
+   }
+
+   return 0;
+}
+
 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 {
struct intel_engine_cs *engine = rq->engine;
 
if (mode & EMIT_FLUSH) {
u32 flags = 0;
+   int err;
u32 *cs;
 
+   err = mtl_dummy_pipe_control(rq);
+   if (err)
+   return err;
+
flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -217,6 +243,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE) {
u32 flags = 0;
u32 *cs, count;
+   int err;
+
+   err = mtl_dummy_pipe_control(rq);
+   if (err)
+   return err;
 
flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -733,6 +764,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request 
*rq, u32 *cs)
 PIPE_CONTROL_DC_FLUSH_ENABLE |
 PIPE_CONTROL_FLUSH_ENABLE);
 
+   /* Wa_14016712196 */
+   if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+   IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+   /* dummy PIPE_CONTROL + depth flush */
+   cs = gen12_emit_pipe_control(cs, 0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
+
if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 
50))
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
-- 
2.25.1