[Intel-gfx] [PATCH i-g-t v5 02/11] tests/perf: add per context filtering test for gen8+
From: Robert Bragg Signed-off-by: Robert Bragg Signed-off-by: Lionel Landwerlin --- tests/perf.c | 777 --- 1 file changed, 745 insertions(+), 32 deletions(-) diff --git a/tests/perf.c b/tests/perf.c index f89a235e..8644e252 100644 --- a/tests/perf.c +++ b/tests/perf.c @@ -48,7 +48,9 @@ IGT_TEST_DESCRIPTION("Test the i915 perf metrics streaming interface"); #define OAREPORT_REASON_MASK 0x3f #define OAREPORT_REASON_SHIFT 19 #define OAREPORT_REASON_TIMER (1<<0) +#define OAREPORT_REASON_INTERNAL (3<<1) #define OAREPORT_REASON_CTX_SWITCH (1<<3) +#define OAREPORT_REASON_GO (1<<4) #define OAREPORT_REASON_CLK_RATIO (1<<5) #define GFX_OP_PIPE_CONTROL ((3 << 29) | (3 << 27) | (2 << 24)) @@ -574,6 +576,22 @@ oa_exponent_to_ns(int exponent) return 10ULL * (2ULL << exponent) / timestamp_frequency; } +static bool +oa_report_ctx_is_valid(uint32_t *report) +{ + if (IS_HASWELL(devid)) { + return false; /* TODO */ + } else if (IS_GEN8(devid)) { + return report[0] & (1ul << 25); + } else if (IS_GEN9(devid)) { + return report[0] & (1ul << 16); + } + + /* Need to update this function for newer Gen. */ + igt_assert(!"reached"); +} + + static void hsw_sanity_check_render_basic_reports(uint32_t *oa_report0, uint32_t *oa_report1, enum drm_i915_oa_format fmt) @@ -678,6 +696,100 @@ gen8_40bit_a_delta(uint64_t value0, uint64_t value1) return value1 - value0; } +static void +accumulate_uint32(size_t offset, + uint32_t *report0, + uint32_t *report1, + uint64_t *delta) +{ + uint32_t value0 = *(uint32_t *)(((uint8_t *)report0) + offset); + uint32_t value1 = *(uint32_t *)(((uint8_t *)report1) + offset); + + *delta += (uint32_t)(value1 - value0); +} + +static void +accumulate_uint40(int a_index, + uint32_t *report0, + uint32_t *report1, + enum drm_i915_oa_format format, + uint64_t *delta) +{ + uint64_t value0 = gen8_read_40bit_a_counter(report0, format, a_index), +value1 = gen8_read_40bit_a_counter(report1, format, a_index); + + *delta += gen8_40bit_a_delta(value0, value1); +} + +static void +accumulate_reports(struct accumulator *accumulator, + uint32_t *start, + uint32_t *end) +{ + enum drm_i915_oa_format format = accumulator->format; + uint64_t *deltas = accumulator->deltas; + int idx = 0; + + if (intel_gen(devid) >= 8) { + /* timestamp */ + accumulate_uint32(4, start, end, deltas + idx++); + + /* clock cycles */ + accumulate_uint32(12, start, end, deltas + idx++); + } else { + /* timestamp */ + accumulate_uint32(4, start, end, deltas + idx++); + } + + for (int i = 0; i < oa_formats[format].n_a40; i++) + accumulate_uint40(i, start, end, format, deltas + idx++); + + for (int i = 0; i < oa_formats[format].n_a; i++) { + accumulate_uint32(oa_formats[format].a_off + 4 * i, + start, end, deltas + idx++); + } + + for (int i = 0; i < oa_formats[format].n_b; i++) { + accumulate_uint32(oa_formats[format].b_off + 4 * i, + start, end, deltas + idx++); + } + + for (int i = 0; i < oa_formats[format].n_c; i++) { + accumulate_uint32(oa_formats[format].c_off + 4 * i, + start, end, deltas + idx++); + } +} + +static void +accumulator_print(struct accumulator *accumulator, const char *title) +{ + enum drm_i915_oa_format format = accumulator->format; + uint64_t *deltas = accumulator->deltas; + int idx = 0; + + igt_debug("%s:\n", title); + if (intel_gen(devid) >= 8) { + igt_debug("\ttime delta = %lu\n", deltas[idx++]); + igt_debug("\tclock cycle delta = %lu\n", deltas[idx++]); + + for (int i = 0; i < oa_formats[format].n_a40; i++) + igt_debug("\tA%u = %lu\n", i, deltas[idx++]); + } else { + igt_debug("\ttime delta = %lu\n", deltas[idx++]); + } + + for (int i = 0; i < oa_formats[format].n_a; i++) { + int a_id = oa_formats[format].first_a + i; + igt_debug("\tA%u = %lu\n", a_id, deltas[idx++]); + } + + for (int i = 0; i < oa_formats[format].n_a; i++) + igt_debug("\tB%u = %lu\n", i, deltas[idx++]); + + for (int i = 0; i < oa_formats[format].n_c; i++) + igt_debug("\tC%u = %lu\n", i, deltas[idx++]); +} + /* The TestOa metric set is designed so */ static void gen8_sanity_check_test_
Re: [Intel-gfx] [PATCH i-g-t v5 02/11] tests/perf: add per context filtering test for gen8+
Hey Matt, Any feedback on this patch? On 31/08/17 11:35, Lionel Landwerlin wrote: From: Robert Bragg Signed-off-by: Robert Bragg Signed-off-by: Lionel Landwerlin --- tests/perf.c | 777 --- 1 file changed, 745 insertions(+), 32 deletions(-) diff --git a/tests/perf.c b/tests/perf.c index f89a235e..8644e252 100644 --- a/tests/perf.c +++ b/tests/perf.c @@ -48,7 +48,9 @@ IGT_TEST_DESCRIPTION("Test the i915 perf metrics streaming interface"); #define OAREPORT_REASON_MASK 0x3f #define OAREPORT_REASON_SHIFT 19 #define OAREPORT_REASON_TIMER (1<<0) +#define OAREPORT_REASON_INTERNAL (3<<1) #define OAREPORT_REASON_CTX_SWITCH (1<<3) +#define OAREPORT_REASON_GO (1<<4) #define OAREPORT_REASON_CLK_RATIO (1<<5) #define GFX_OP_PIPE_CONTROL ((3 << 29) | (3 << 27) | (2 << 24)) @@ -574,6 +576,22 @@ oa_exponent_to_ns(int exponent) return 10ULL * (2ULL << exponent) / timestamp_frequency; } +static bool +oa_report_ctx_is_valid(uint32_t *report) +{ + if (IS_HASWELL(devid)) { + return false; /* TODO */ + } else if (IS_GEN8(devid)) { + return report[0] & (1ul << 25); + } else if (IS_GEN9(devid)) { + return report[0] & (1ul << 16); + } + + /* Need to update this function for newer Gen. */ + igt_assert(!"reached"); +} + + static void hsw_sanity_check_render_basic_reports(uint32_t *oa_report0, uint32_t *oa_report1, enum drm_i915_oa_format fmt) @@ -678,6 +696,100 @@ gen8_40bit_a_delta(uint64_t value0, uint64_t value1) return value1 - value0; } +static void +accumulate_uint32(size_t offset, + uint32_t *report0, + uint32_t *report1, + uint64_t *delta) +{ + uint32_t value0 = *(uint32_t *)(((uint8_t *)report0) + offset); + uint32_t value1 = *(uint32_t *)(((uint8_t *)report1) + offset); + + *delta += (uint32_t)(value1 - value0); +} + +static void +accumulate_uint40(int a_index, + uint32_t *report0, + uint32_t *report1, + enum drm_i915_oa_format format, + uint64_t *delta) +{ + uint64_t value0 = gen8_read_40bit_a_counter(report0, format, a_index), +value1 = gen8_read_40bit_a_counter(report1, format, a_index); + + *delta += gen8_40bit_a_delta(value0, value1); +} + +static void +accumulate_reports(struct accumulator *accumulator, + uint32_t *start, + uint32_t *end) +{ + enum drm_i915_oa_format format = accumulator->format; + uint64_t *deltas = accumulator->deltas; + int idx = 0; + + if (intel_gen(devid) >= 8) { + /* timestamp */ + accumulate_uint32(4, start, end, deltas + idx++); + + /* clock cycles */ + accumulate_uint32(12, start, end, deltas + idx++); + } else { + /* timestamp */ + accumulate_uint32(4, start, end, deltas + idx++); + } + + for (int i = 0; i < oa_formats[format].n_a40; i++) + accumulate_uint40(i, start, end, format, deltas + idx++); + + for (int i = 0; i < oa_formats[format].n_a; i++) { + accumulate_uint32(oa_formats[format].a_off + 4 * i, + start, end, deltas + idx++); + } + + for (int i = 0; i < oa_formats[format].n_b; i++) { + accumulate_uint32(oa_formats[format].b_off + 4 * i, + start, end, deltas + idx++); + } + + for (int i = 0; i < oa_formats[format].n_c; i++) { + accumulate_uint32(oa_formats[format].c_off + 4 * i, + start, end, deltas + idx++); + } +} + +static void +accumulator_print(struct accumulator *accumulator, const char *title) +{ + enum drm_i915_oa_format format = accumulator->format; + uint64_t *deltas = accumulator->deltas; + int idx = 0; + + igt_debug("%s:\n", title); + if (intel_gen(devid) >= 8) { + igt_debug("\ttime delta = %lu\n", deltas[idx++]); + igt_debug("\tclock cycle delta = %lu\n", deltas[idx++]); + + for (int i = 0; i < oa_formats[format].n_a40; i++) + igt_debug("\tA%u = %lu\n", i, deltas[idx++]); + } else { + igt_debug("\ttime delta = %lu\n", deltas[idx++]); + } + + for (int i = 0; i < oa_formats[format].n_a; i++) { + int a_id = oa_formats[format].first_a + i; + igt_debug("\tA%u = %lu\n", a_id, deltas[idx++]); + } + + for (int i = 0; i < oa_formats[format].n_a; i++) + igt_debug("\tB%u = %lu\n", i, deltas[idx++]); + + for (int i = 0; i < oa_formats[format].n_c; i++) + igt_debug("\tC%u = %lu\n",