[Intel-gfx] [PATCH v1 3/4] drm/i915:bxt: Enable Pooled EU support
This mode allows to assign EUs to pools.
The command to enable this mode is sent in auxiliary golden context batch
as this is only issued once with each context initialization. Thanks to
Mika for the preliminary review.
Cc: Mika Kuoppala mika.kuopp...@intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Armin Reese armin.c.re...@intel.com
Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com
---
drivers/gpu/drm/i915/i915_gem_render_state.c | 15 +++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index b86e382..a41a1b6 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -84,6 +84,7 @@ free_gem:
static int render_state_setup(struct render_state *so)
{
+ struct drm_device *dev = so-obj-base.dev;
const struct intel_renderstate_rodata *rodata = so-rodata;
unsigned int i = 0, reloc_index = 0;
struct page *page;
@@ -125,6 +126,20 @@ static int render_state_setup(struct render_state *so)
so-aux_batch_offset = i * sizeof(u32);
+ if (IS_BROXTON(dev)) {
+ u32 pool_config = 0;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
+ OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
+ if (dev_priv-info.subslice_total == 3)
+ pool_config = 0x00777000;
+ OUT_BATCH(d, i, pool_config);
+ OUT_BATCH(d, i, 0);
+ OUT_BATCH(d, i, 0);
+ OUT_BATCH(d, i, 0);
+ }
+
OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
so-aux_batch_size = (i * sizeof(u32)) - so-aux_batch_offset;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a2ffad..e052499 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -379,6 +379,8 @@
*/
#define GFX_INSTR(opcode, flags) ((0x3 29) | ((opcode) 24) | (flags))
+#define GEN9_MEDIA_POOL_STATE ((0x3 29) | (0x2 27) | (0x5 16) | 4)
+#define GEN9_MEDIA_POOL_ENABLE (1 31)
#define GFX_OP_RASTER_RULES((0x329)|(0x724))
#define GFX_OP_SCISSOR ((0x329)|(0x1c24)|(0x1019))
#define SC_UPDATE_SCISSOR (0x11)
--
1.9.1
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Re: [Intel-gfx] [PATCH v1 3/4] drm/i915:bxt: Enable Pooled EU support
On Fri, Jul 17, 2015 at 05:08:53PM +0100, Arun Siluvery wrote: This mode allows to assign EUs to pools. The command to enable this mode is sent in auxiliary golden context batch as this is only issued once with each context initialization. Thanks to Mika for the preliminary review. A quick explanation for why this has to be in the kernel would be nice. Privileged instruction? Not fond of the split between this and patch 4. Patch 4 intoduces one feature flag that looks different to the one we use here to enable support. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 3/4] drm/i915:bxt: Enable Pooled EU support
On Fri, Jul 17, 2015 at 05:54:20PM +0100, Siluvery, Arun wrote: On 17/07/2015 17:27, Chris Wilson wrote: On Fri, Jul 17, 2015 at 05:08:53PM +0100, Arun Siluvery wrote: This mode allows to assign EUs to pools. The command to enable this mode is sent in auxiliary golden context batch as this is only issued once with each context initialization. Thanks to Mika for the preliminary review. A quick explanation for why this has to be in the kernel would be nice. Privileged instruction? This purpose of auxiliary batch is explained in patch2, but I can add some explanation about this one also. Here, I am looking for an explanation of why these commands in particular are desired. Mika's short explanation that must be the same for all contexts on the system is sufficient. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 3/4] drm/i915:bxt: Enable Pooled EU support
Chris Wilson ch...@chris-wilson.co.uk writes: On Fri, Jul 17, 2015 at 05:08:53PM +0100, Arun Siluvery wrote: This mode allows to assign EUs to pools. The command to enable this mode is sent in auxiliary golden context batch as this is only issued once with each context initialization. Thanks to Mika for the preliminary review. A quick explanation for why this has to be in the kernel would be nice. Privileged instruction? The pooled mode is global. Once set, it has to stay same across all contexts until subsequent fw reset. -Mika Not fond of the split between this and patch 4. Patch 4 intoduces one feature flag that looks different to the one we use here to enable support. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 3/4] drm/i915:bxt: Enable Pooled EU support
On 17/07/2015 17:27, Chris Wilson wrote: On Fri, Jul 17, 2015 at 05:08:53PM +0100, Arun Siluvery wrote: This mode allows to assign EUs to pools. The command to enable this mode is sent in auxiliary golden context batch as this is only issued once with each context initialization. Thanks to Mika for the preliminary review. A quick explanation for why this has to be in the kernel would be nice. Privileged instruction? This purpose of auxiliary batch is explained in patch2, but I can add some explanation about this one also. Not fond of the split between this and patch 4. Patch 4 intoduces one feature flag that looks different to the one we use here to enable support. I will patch4 as separate as it deals with libdrm changes but use the feature flag in this one. regards Arun -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
