Re: [Intel-gfx] [PATCH v2 01/10] drm/i915/skl: Move per-pipe ddb allocations into crtc states
Em Sex, 2016-10-07 às 20:11 -0400, Lyude escreveu: > First part of cleaning up all of the skl watermark code. This moves > the > structures for storing the ddb allocations of each pipe into > intel_crtc_state, along with moving the structures for storing the > current ddb allocations active on hardware into intel_crtc. > > Changes since v1: > - Don't replace alloc->start = alloc->end = 0; > > Signed-off-by: LyudeReviewed-by: Paulo Zanoni > Reviewed-by: Maarten Lankhorst > Cc: Ville Syrjälä > Cc: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_drv.h | 1 - > drivers/gpu/drm/i915/intel_display.c | 16 --- > drivers/gpu/drm/i915/intel_drv.h | 8 +--- > drivers/gpu/drm/i915/intel_pm.c | 40 +++--- > -- > 4 files changed, 30 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > b/drivers/gpu/drm/i915/i915_drv.h > index a219a35..bb2de8d 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1637,7 +1637,6 @@ static inline bool skl_ddb_entry_equal(const > struct skl_ddb_entry *e1, > } > > struct skl_ddb_allocation { > - struct skl_ddb_entry pipe[I915_MAX_PIPES]; > struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; > /* packed/uv */ > struct skl_ddb_entry > y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; > }; > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index a366656..17733af 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -14235,12 +14235,11 @@ static void skl_update_crtcs(struct > drm_atomic_state *state, > unsigned int *crtc_vblank_mask) > { > struct drm_device *dev = state->dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > struct intel_atomic_state *intel_state = > to_intel_atomic_state(state); > struct drm_crtc *crtc; > + struct intel_crtc *intel_crtc; > struct drm_crtc_state *old_crtc_state; > - struct skl_ddb_allocation *new_ddb = _state- > >wm_results.ddb; > - struct skl_ddb_allocation *cur_ddb = _priv- > >wm.skl_hw.ddb; > + struct intel_crtc_state *cstate; > unsigned int updated = 0; > bool progress; > enum pipe pipe; > @@ -14258,12 +14257,14 @@ static void skl_update_crtcs(struct > drm_atomic_state *state, > for_each_crtc_in_state(state, crtc, old_crtc_state, > i) { > bool vbl_wait = false; > unsigned int cmask = drm_crtc_mask(crtc); > - pipe = to_intel_crtc(crtc)->pipe; > + > + intel_crtc = to_intel_crtc(crtc); > + cstate = to_intel_crtc_state(crtc->state); > + pipe = intel_crtc->pipe; > > if (updated & cmask || !crtc->state->active) > continue; > - if (skl_ddb_allocation_overlaps(state, > cur_ddb, new_ddb, > - pipe)) > + if (skl_ddb_allocation_overlaps(state, > intel_crtc)) > continue; > > updated |= cmask; > @@ -14274,7 +14275,8 @@ static void skl_update_crtcs(struct > drm_atomic_state *state, > * then we need to wait for a vblank to pass > for the > * new ddb allocation to take effect. > */ > - if (!skl_ddb_allocation_equals(cur_ddb, > new_ddb, pipe) && > + if (!skl_ddb_entry_equal( > >wm.skl.ddb, > + _crtc- > >hw_ddb) && > !crtc->state->active_changed && > intel_state->wm_results.dirty_pipes != > updated) > vbl_wait = true; > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index f48e79a..35ba282 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -496,6 +496,7 @@ struct intel_crtc_wm_state { > struct { > /* gen9+ only needs 1-step wm programming */ > struct skl_pipe_wm optimal; > + struct skl_ddb_entry ddb; > > /* cached plane data rate */ > unsigned plane_data_rate[I915_MAX_PLANES]; > @@ -733,6 +734,9 @@ struct intel_crtc { > bool cxsr_allowed; > } wm; > > + /* gen9+: ddb allocation currently being used */ > + struct skl_ddb_entry hw_ddb; > + > int scanline_offset; > > struct { > @@ -1755,9 +1759,7 @@ bool skl_ddb_allocation_equals(const struct > skl_ddb_allocation *old, >
[Intel-gfx] [PATCH v2 01/10] drm/i915/skl: Move per-pipe ddb allocations into crtc states
First part of cleaning up all of the skl watermark code. This moves the structures for storing the ddb allocations of each pipe into intel_crtc_state, along with moving the structures for storing the current ddb allocations active on hardware into intel_crtc. Changes since v1: - Don't replace alloc->start = alloc->end = 0; Signed-off-by: LyudeReviewed-by: Maarten Lankhorst Cc: Ville Syrjälä Cc: Paulo Zanoni --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/intel_display.c | 16 --- drivers/gpu/drm/i915/intel_drv.h | 8 +--- drivers/gpu/drm/i915/intel_pm.c | 40 +++- 4 files changed, 30 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a219a35..bb2de8d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1637,7 +1637,6 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, } struct skl_ddb_allocation { - struct skl_ddb_entry pipe[I915_MAX_PIPES]; struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; }; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a366656..17733af 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14235,12 +14235,11 @@ static void skl_update_crtcs(struct drm_atomic_state *state, unsigned int *crtc_vblank_mask) { struct drm_device *dev = state->dev; - struct drm_i915_private *dev_priv = to_i915(dev); struct intel_atomic_state *intel_state = to_intel_atomic_state(state); struct drm_crtc *crtc; + struct intel_crtc *intel_crtc; struct drm_crtc_state *old_crtc_state; - struct skl_ddb_allocation *new_ddb = _state->wm_results.ddb; - struct skl_ddb_allocation *cur_ddb = _priv->wm.skl_hw.ddb; + struct intel_crtc_state *cstate; unsigned int updated = 0; bool progress; enum pipe pipe; @@ -14258,12 +14257,14 @@ static void skl_update_crtcs(struct drm_atomic_state *state, for_each_crtc_in_state(state, crtc, old_crtc_state, i) { bool vbl_wait = false; unsigned int cmask = drm_crtc_mask(crtc); - pipe = to_intel_crtc(crtc)->pipe; + + intel_crtc = to_intel_crtc(crtc); + cstate = to_intel_crtc_state(crtc->state); + pipe = intel_crtc->pipe; if (updated & cmask || !crtc->state->active) continue; - if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb, - pipe)) + if (skl_ddb_allocation_overlaps(state, intel_crtc)) continue; updated |= cmask; @@ -14274,7 +14275,8 @@ static void skl_update_crtcs(struct drm_atomic_state *state, * then we need to wait for a vblank to pass for the * new ddb allocation to take effect. */ - if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) && + if (!skl_ddb_entry_equal(>wm.skl.ddb, +_crtc->hw_ddb) && !crtc->state->active_changed && intel_state->wm_results.dirty_pipes != updated) vbl_wait = true; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f48e79a..35ba282 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -496,6 +496,7 @@ struct intel_crtc_wm_state { struct { /* gen9+ only needs 1-step wm programming */ struct skl_pipe_wm optimal; + struct skl_ddb_entry ddb; /* cached plane data rate */ unsigned plane_data_rate[I915_MAX_PLANES]; @@ -733,6 +734,9 @@ struct intel_crtc { bool cxsr_allowed; } wm; + /* gen9+: ddb allocation currently being used */ + struct skl_ddb_entry hw_ddb; + int scanline_offset; struct { @@ -1755,9 +1759,7 @@ bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old, const struct skl_ddb_allocation *new, enum pipe pipe); bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state, -const struct skl_ddb_allocation *old, -