Re: [Intel-gfx] [PATCH v2 03/11] drm/i915/psr: Set PSR CRC verification bit in sink inside PSR1 block
On Fri, 2018-11-30 at 15:54 -0800, Dhinakaran Pandiyan wrote: > On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote: > > As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {' > > and this bit is only set for PSR1 move it to that block to make it > > more easy to read. > > > > Cc: Dhinakaran Pandiyan > > Cc: Rodrigo Vivi > > Signed-off-by: José Roberto de Souza > > --- > > drivers/gpu/drm/i915/intel_psr.c | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 8515f4a6f4f1..b04472e637c8 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -398,10 +398,11 @@ static void intel_psr_enable_sink(struct > > intel_dp *intel_dp) > > } else { > > if (dev_priv->psr.link_standby) > > dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; > > + > > + if (INTEL_GEN(dev_priv) >= 8) > > + dpcd_val |= DP_PSR_CRC_VERIFICATION; > > } > > > > - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8) > > - dpcd_val |= DP_PSR_CRC_VERIFICATION; > > drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > > > drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER, > > DP_SET_POWER_D0); > > Do we need this DPCD write? The panel should already be awake by this > point, I think it's worth removing it if there's no regression. > > Your change in this patch looks good, so > Reviewed-by: Dhinakaran Pandiyan > Added to the list to things to TODO. Thanks for the review. > > > signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 03/11] drm/i915/psr: Set PSR CRC verification bit in sink inside PSR1 block
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote: > As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {' > and this bit is only set for PSR1 move it to that block to make it > more easy to read. > > Cc: Dhinakaran Pandiyan > Cc: Rodrigo Vivi > Signed-off-by: José Roberto de Souza > --- > drivers/gpu/drm/i915/intel_psr.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index 8515f4a6f4f1..b04472e637c8 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -398,10 +398,11 @@ static void intel_psr_enable_sink(struct > intel_dp *intel_dp) > } else { > if (dev_priv->psr.link_standby) > dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; > + > + if (INTEL_GEN(dev_priv) >= 8) > + dpcd_val |= DP_PSR_CRC_VERIFICATION; > } > > - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8) > - dpcd_val |= DP_PSR_CRC_VERIFICATION; > drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER, > DP_SET_POWER_D0); Do we need this DPCD write? The panel should already be awake by this point, I think it's worth removing it if there's no regression. Your change in this patch looks good, so Reviewed-by: Dhinakaran Pandiyan ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 03/11] drm/i915/psr: Set PSR CRC verification bit in sink inside PSR1 block
As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {' and this bit is only set for PSR1 move it to that block to make it more easy to read. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 8515f4a6f4f1..b04472e637c8 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -398,10 +398,11 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) } else { if (dev_priv->psr.link_standby) dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; + + if (INTEL_GEN(dev_priv) >= 8) + dpcd_val |= DP_PSR_CRC_VERIFICATION; } - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8) - dpcd_val |= DP_PSR_CRC_VERIFICATION; drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val); drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx