Re: [Intel-gfx] [PATCH v2 04/10] drm/i915: Unduplicate CHV phy-releated pre pll enabling code

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:47PM +0300, Ander Conselvan de Oliveira wrote:
> The same logic is used for DP and HDMI so move it to intel_dpio_phy.c.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> 

Reviewed-by: Jim Bride 

> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  1 +
>  drivers/gpu/drm/i915/intel_dp.c   | 83 
> +--
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 81 ++
>  drivers/gpu/drm/i915/intel_drv.h  |  5 +++
>  drivers/gpu/drm/i915/intel_hdmi.c | 74 +--
>  5 files changed, 89 insertions(+), 155 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fe40761..19bfe04 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3560,6 +3560,7 @@ void chv_set_phy_signal_level(struct intel_encoder 
> *encoder,
> bool uniq_trans_scale);
>  void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> bool reset);
> +void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4d63071..dd62bf0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -131,11 +131,6 @@ static void vlv_steal_power_sequencer(struct drm_device 
> *dev,
> enum pipe pipe);
>  static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>  
> -static unsigned int intel_dp_unused_lane_mask(int lane_count)
> -{
> - return ~((1 << lane_count) - 1) & 0xf;
> -}
> -
>  static int
>  intel_dp_max_link_bw(struct intel_dp  *intel_dp)
>  {
> @@ -2945,85 +2940,9 @@ static void chv_pre_enable_dp(struct intel_encoder 
> *encoder)
>  
>  static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  {
> - struct intel_digital_port *dport = enc_to_dig_port(>base);
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc =
> - to_intel_crtc(encoder->base.crtc);
> - enum dpio_channel ch = vlv_dport_to_channel(dport);
> - enum pipe pipe = intel_crtc->pipe;
> - unsigned int lane_mask =
> - intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
> - u32 val;
> -
>   intel_dp_prepare(encoder);
>  
> - /*
> -  * Must trick the second common lane into life.
> -  * Otherwise we can't even access the PLL.
> -  */
> - if (ch == DPIO_CH0 && pipe == PIPE_B)
> - dport->release_cl2_override =
> - !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, 
> true);
> -
> - chv_phy_powergate_lanes(encoder, true, lane_mask);
> -
> - mutex_lock(_priv->sb_lock);
> -
> - /* Assert data lane reset */
> - chv_data_lane_soft_reset(encoder, true);
> -
> - /* program left/right clock distribution */
> - if (pipe != PIPE_B) {
> - val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> - val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> - if (ch == DPIO_CH0)
> - val |= CHV_BUFLEFTENA1_FORCE;
> - if (ch == DPIO_CH1)
> - val |= CHV_BUFRIGHTENA1_FORCE;
> - vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> - } else {
> - val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> - val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> - if (ch == DPIO_CH0)
> - val |= CHV_BUFLEFTENA2_FORCE;
> - if (ch == DPIO_CH1)
> - val |= CHV_BUFRIGHTENA2_FORCE;
> - vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> - }
> -
> - /* program clock channel usage */
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
> - val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> - if (pipe != PIPE_B)
> - val &= ~CHV_PCS_USEDCLKCHANNEL;
> - else
> - val |= CHV_PCS_USEDCLKCHANNEL;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
> -
> - if (intel_crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
> - val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> - if (pipe != PIPE_B)
> - val &= ~CHV_PCS_USEDCLKCHANNEL;
> - else
> - val |= CHV_PCS_USEDCLKCHANNEL;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
> - }
> -
> - /*
> -  * This a a bit weird since generally CL
> -  * matches the pipe, but here we need to
> -  * pick the CL based on the 

[Intel-gfx] [PATCH v2 04/10] drm/i915: Unduplicate CHV phy-releated pre pll enabling code

[Ander Conselvan de Oliveira]

The same logic is used for DP and HDMI so move it to intel_dpio_phy.c.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/intel_dp.c   | 83 +--
 drivers/gpu/drm/i915/intel_dpio_phy.c | 81 ++
 drivers/gpu/drm/i915/intel_drv.h  |  5 +++
 drivers/gpu/drm/i915/intel_hdmi.c | 74 +--
 5 files changed, 89 insertions(+), 155 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fe40761..19bfe04 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3560,6 +3560,7 @@ void chv_set_phy_signal_level(struct intel_encoder 
*encoder,
  bool uniq_trans_scale);
 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
  bool reset);
+void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4d63071..dd62bf0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -131,11 +131,6 @@ static void vlv_steal_power_sequencer(struct drm_device 
*dev,
  enum pipe pipe);
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 
-static unsigned int intel_dp_unused_lane_mask(int lane_count)
-{
-   return ~((1 << lane_count) - 1) & 0xf;
-}
-
 static int
 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 {
@@ -2945,85 +2940,9 @@ static void chv_pre_enable_dp(struct intel_encoder 
*encoder)
 
 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
 {
-   struct intel_digital_port *dport = enc_to_dig_port(>base);
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   struct intel_crtc *intel_crtc =
-   to_intel_crtc(encoder->base.crtc);
-   enum dpio_channel ch = vlv_dport_to_channel(dport);
-   enum pipe pipe = intel_crtc->pipe;
-   unsigned int lane_mask =
-   intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
-   u32 val;
-
intel_dp_prepare(encoder);
 
-   /*
-* Must trick the second common lane into life.
-* Otherwise we can't even access the PLL.
-*/
-   if (ch == DPIO_CH0 && pipe == PIPE_B)
-   dport->release_cl2_override =
-   !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, 
true);
-
-   chv_phy_powergate_lanes(encoder, true, lane_mask);
-
-   mutex_lock(_priv->sb_lock);
-
-   /* Assert data lane reset */
-   chv_data_lane_soft_reset(encoder, true);
-
-   /* program left/right clock distribution */
-   if (pipe != PIPE_B) {
-   val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
-   val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-   if (ch == DPIO_CH0)
-   val |= CHV_BUFLEFTENA1_FORCE;
-   if (ch == DPIO_CH1)
-   val |= CHV_BUFRIGHTENA1_FORCE;
-   vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
-   } else {
-   val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
-   val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-   if (ch == DPIO_CH0)
-   val |= CHV_BUFLEFTENA2_FORCE;
-   if (ch == DPIO_CH1)
-   val |= CHV_BUFRIGHTENA2_FORCE;
-   vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
-   }
-
-   /* program clock channel usage */
-   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
-   val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-   if (pipe != PIPE_B)
-   val &= ~CHV_PCS_USEDCLKCHANNEL;
-   else
-   val |= CHV_PCS_USEDCLKCHANNEL;
-   vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
-
-   if (intel_crtc->config->lane_count > 2) {
-   val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
-   val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-   if (pipe != PIPE_B)
-   val &= ~CHV_PCS_USEDCLKCHANNEL;
-   else
-   val |= CHV_PCS_USEDCLKCHANNEL;
-   vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
-   }
-
-   /*
-* This a a bit weird since generally CL
-* matches the pipe, but here we need to
-* pick the CL based on the port.
-*/
-   val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
-   if (pipe != PIPE_B)
-   val &= ~CHV_CMN_USEDCLKCHANNEL;
-   else
-   val |= CHV_CMN_USEDCLKCHANNEL;
-