Re: [Intel-gfx] [PATCH v2 04/13] drm/i915/tgl: Add dkl phy registers
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> From: Vandita Kulkarni
>
> These are the registers needed to program Dekel phy. Some register
> definitions will be reused from MG PHY definitions, so adding a
> comment on those.
>
> Bspec: 49295
>
> Signed-off-by: Vandita Kulkarni
> Signed-off-by: Clinton A Taylor
> Signed-off-by: Lucas De Marchi
> Signed-off-by: José Roberto de Souza
You can turn my s-o-b into
Reviewed-by: Lucas De Marchi
(s-o-b was only here since I had sent the previous version)
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 162
> 1 file changed, 162 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ee5626579263..32f98d0e0e9c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10104,6 +10104,168 @@ enum skl_power_gate {
>_TGL_DPLL1_CFGCR1, \
>_TGL_TBTPLL_CFGCR1)
>
> +#define _DKL_PHY1_BASE 0x168000
> +#define _DKL_PHY2_BASE 0x169000
> +#define _DKL_PHY3_BASE 0x16A000
> +#define _DKL_PHY4_BASE 0x16B000
> +#define _DKL_PHY5_BASE 0x16C000
> +#define _DKL_PHY6_BASE 0x16D000
> +
> +/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
> +#define _DKL_PLL_DIV0 0x200
> +#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
> +#define DKL_PLL_DIV0_INTEG_COEFF_MASK(0x1F << 16)
> +#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
> +#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
> +#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8)
> +#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
> +#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
> +#define DKL_PLL_DIV0_FBDIV_INT(x)((x) << 0)
> +#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
> +#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> + _DKL_PLL_DIV0)
> +
> +#define _DKL_PLL_DIV1 0x204
> +#define DKL_PLL_DIV1_IREF_TRIM(x)((x) << 16)
> +#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
> +#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
> +#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
> +#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> + _DKL_PLL_DIV1)
> +
> +#define _DKL_PLL_SSC 0x210
> +#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
> +#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
> +#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
> +#define DKL_PLL_SSC_STEP_LEN_MASK(0xFF << 16)
> +#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
> +#define DKL_PLL_SSC_STEP_NUM_MASK(0x7 << 11)
> +#define DKL_PLL_SSC_EN (1 << 9)
> +#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> + _DKL_PLL_SSC)
> +
> +#define _DKL_PLL_BIAS 0x214
> +#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
> +#define DKL_PLL_BIAS_FBDIV_SHIFT (8)
> +#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
> +#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3F << DKL_PLL_BIAS_FBDIV_SHIFT)
> +#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> + _DKL_PLL_BIAS)
> +
> +#define _DKL_PLL_TDC_COLDST_BIAS 0x218
> +#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
> +#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
> +#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
> +#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
> +#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
> +_DKL_PHY1_BASE, \
> +_DKL_PHY2_BASE) + \
> +_DKL_PLL_TDC_COLDST_BIAS)
> +
> +#define _DKL_REFCLKIN_CTL 0x12C
> +/* Bits are the same as MG_REFCLKIN_CTL */
> +#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
> + _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> +
[Intel-gfx] [PATCH v2 04/13] drm/i915/tgl: Add dkl phy registers
From: Vandita Kulkarni
These are the registers needed to program Dekel phy. Some register
definitions will be reused from MG PHY definitions, so adding a
comment on those.
Bspec: 49295
Signed-off-by: Vandita Kulkarni
Signed-off-by: Clinton A Taylor
Signed-off-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 162
1 file changed, 162 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ee5626579263..32f98d0e0e9c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10104,6 +10104,168 @@ enum skl_power_gate {
_TGL_DPLL1_CFGCR1, \
_TGL_TBTPLL_CFGCR1)
+#define _DKL_PHY1_BASE 0x168000
+#define _DKL_PHY2_BASE 0x169000
+#define _DKL_PHY3_BASE 0x16A000
+#define _DKL_PHY4_BASE 0x16B000
+#define _DKL_PHY5_BASE 0x16C000
+#define _DKL_PHY6_BASE 0x16D000
+
+/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
+#define _DKL_PLL_DIV0 0x200
+#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
+#define DKL_PLL_DIV0_INTEG_COEFF_MASK(0x1F << 16)
+#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
+#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
+#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8)
+#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
+#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
+#define DKL_PLL_DIV0_FBDIV_INT(x)((x) << 0)
+#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
+#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV0)
+
+#define _DKL_PLL_DIV1 0x204
+#define DKL_PLL_DIV1_IREF_TRIM(x)((x) << 16)
+#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
+#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
+#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
+#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV1)
+
+#define _DKL_PLL_SSC 0x210
+#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
+#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
+#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
+#define DKL_PLL_SSC_STEP_LEN_MASK(0xFF << 16)
+#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
+#define DKL_PLL_SSC_STEP_NUM_MASK(0x7 << 11)
+#define DKL_PLL_SSC_EN (1 << 9)
+#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_SSC)
+
+#define _DKL_PLL_BIAS 0x214
+#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
+#define DKL_PLL_BIAS_FBDIV_SHIFT (8)
+#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
+#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3F << DKL_PLL_BIAS_FBDIV_SHIFT)
+#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_BIAS)
+
+#define _DKL_PLL_TDC_COLDST_BIAS 0x218
+#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
+#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
+#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
+#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
+#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
+_DKL_PHY1_BASE, \
+_DKL_PHY2_BASE) + \
+_DKL_PLL_TDC_COLDST_BIAS)
+
+#define _DKL_REFCLKIN_CTL 0x12C
+/* Bits are the same as MG_REFCLKIN_CTL */
+#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_REFCLKIN_CTL)
+
+#define _DKL_CLKTOP2_HSCLKCTL 0xD4
+/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
+#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_CLKTOP
