Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
> From: Sarvela, Tomi P > > From: Ville Syrjälä > > On Wed, Dec 15, 2021 at 09:05:03AM +, Sarvela, Tomi P wrote: > > > > From: Ville Syrjälä > > > > > > > > On Tue, Dec 14, 2021 at 06:25:43PM +0200, Ville Syrjälä wrote: > > > > > On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote: > > > > > > On Mon, 13 Dec 2021, Ville Syrjala > > wrote: > > > > > > > > > > > > This one is only used in gvt, anyway. And that actually makes me > > wonder > > > > > > if this should be breaking the build. Does CI not have gvt enabled? > > > > > > > > > > Hmm. I thought it was enabled in CI, but maybe not. I've often broken > > > > > gvt with register define changes but I've always caught it before > > > > > pushing. I think I have gvt enabled in my "make sure all commits build > > > > > before I push" test config, so maybe that's where I caught most of > > them. > > > > > > > > > > Tomi, can we enable gvt in ci builds to make sure it at least still > > > > > builds? > > > > > > > > Actually cc Tomi.. > > > > > > GVT-d is enabled and tested by fi-bdw-gvtdvm. > > > > We're talking about the other gvt (whatever it was called), ie. > > CONFIG_DRM_I915_GVT. > > This kconfig entry doesn't exist in default CI kconfig, even as 'is not set' > placeholder: > https://gitlab.freedesktop.org/gfx-ci/i915-infra/- > /blob/master/kconfig/debug > > If the config entry is exact, I'll probably need to upgrade the default config > from 5.13 and add it with requirements. Not today, but maybe soon. kconfigs debug, debug-kasan and debug-gcov have been updated to v5.15 with 'make olddefconfig', and CONFIG_DRM_I915_GVT=y has been set. First CI_DRM to use this kconfig will be CI_DRM_11005. Tomi
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
> From: Ville Syrjälä > On Wed, Dec 15, 2021 at 09:05:03AM +, Sarvela, Tomi P wrote: > > > From: Ville Syrjälä > > > > > > On Tue, Dec 14, 2021 at 06:25:43PM +0200, Ville Syrjälä wrote: > > > > On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote: > > > > > On Mon, 13 Dec 2021, Ville Syrjala > wrote: > > > > > > > > > > This one is only used in gvt, anyway. And that actually makes me > wonder > > > > > if this should be breaking the build. Does CI not have gvt enabled? > > > > > > > > Hmm. I thought it was enabled in CI, but maybe not. I've often broken > > > > gvt with register define changes but I've always caught it before > > > > pushing. I think I have gvt enabled in my "make sure all commits build > > > > before I push" test config, so maybe that's where I caught most of > them. > > > > > > > > Tomi, can we enable gvt in ci builds to make sure it at least still > > > > builds? > > > > > > Actually cc Tomi.. > > > > GVT-d is enabled and tested by fi-bdw-gvtdvm. > > We're talking about the other gvt (whatever it was called), ie. > CONFIG_DRM_I915_GVT. This kconfig entry doesn't exist in default CI kconfig, even as 'is not set' placeholder: https://gitlab.freedesktop.org/gfx-ci/i915-infra/-/blob/master/kconfig/debug If the config entry is exact, I'll probably need to upgrade the default config from 5.13 and add it with requirements. Not today, but maybe soon. Tomi
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
On Wed, Dec 15, 2021 at 09:05:03AM +, Sarvela, Tomi P wrote: > > From: Ville Syrjälä > > > > On Tue, Dec 14, 2021 at 06:25:43PM +0200, Ville Syrjälä wrote: > > > On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote: > > > > On Mon, 13 Dec 2021, Ville Syrjala > > > > wrote: > > > > > > > > This one is only used in gvt, anyway. And that actually makes me wonder > > > > if this should be breaking the build. Does CI not have gvt enabled? > > > > > > Hmm. I thought it was enabled in CI, but maybe not. I've often broken > > > gvt with register define changes but I've always caught it before > > > pushing. I think I have gvt enabled in my "make sure all commits build > > > before I push" test config, so maybe that's where I caught most of them. > > > > > > Tomi, can we enable gvt in ci builds to make sure it at least still > > > builds? > > > > Actually cc Tomi.. > > GVT-d is enabled and tested by fi-bdw-gvtdvm. We're talking about the other gvt (whatever it was called), ie. CONFIG_DRM_I915_GVT. -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
> From: Ville Syrjälä > > On Tue, Dec 14, 2021 at 06:25:43PM +0200, Ville Syrjälä wrote: > > On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote: > > > On Mon, 13 Dec 2021, Ville Syrjala wrote: > > > > > > This one is only used in gvt, anyway. And that actually makes me wonder > > > if this should be breaking the build. Does CI not have gvt enabled? > > > > Hmm. I thought it was enabled in CI, but maybe not. I've often broken > > gvt with register define changes but I've always caught it before > > pushing. I think I have gvt enabled in my "make sure all commits build > > before I push" test config, so maybe that's where I caught most of them. > > > > Tomi, can we enable gvt in ci builds to make sure it at least still > > builds? > > Actually cc Tomi.. GVT-d is enabled and tested by fi-bdw-gvtdvm. Tomi
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
On Tue, 14 Dec 2021, Ville Syrjälä wrote:
> On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote:
>> On Mon, 13 Dec 2021, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > Parametrize ilk+ FBC register offsets based on the FBC instance.
>> >
>> > v2: More intel_ namespace (Jani)
>> >
>> > Cc: Jani Nikula
>> > Signed-off-by: Ville Syrjälä
>>
>> Some questions below, apart from that,
>>
>> Reviewed-by: Jani Nikula
>>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_fbc.c | 34 +---
>> > drivers/gpu/drm/i915/display/intel_fbc.h | 6 +
>> > drivers/gpu/drm/i915/i915_reg.h | 34
>> > drivers/gpu/drm/i915/intel_pm.c | 31 -
>> > 4 files changed, 60 insertions(+), 45 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > index 8be01b93015f..112aafa72253 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > @@ -85,6 +85,8 @@ struct intel_fbc {
>> >struct drm_mm_node compressed_fb;
>> >struct drm_mm_node compressed_llb;
>> >
>> > + enum intel_fbc_id id;
>> > +
>> >u8 limit;
>> >
>> >bool false_color;
>> > @@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
>> >struct intel_fbc_state *fbc_state = >state;
>> >struct drm_i915_private *i915 = fbc->i915;
>> >
>> > - intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
>> > + intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
>> > fbc_state->fence_y_offset);
>> >
>> > - intel_de_write(i915, ILK_DPFC_CONTROL,
>> > + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
>> > DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
>> > }
>> >
>> > @@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
>> >u32 dpfc_ctl;
>> >
>> >/* Disable compression */
>> > - dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
>> > + dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
>> >if (dpfc_ctl & DPFC_CTL_EN) {
>> >dpfc_ctl &= ~DPFC_CTL_EN;
>> > - intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
>> > + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
>> >}
>> > }
>> >
>> > static bool ilk_fbc_is_active(struct intel_fbc *fbc)
>> > {
>> > - return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
>> > + return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) &
>> > DPFC_CTL_EN;
>> > }
>> >
>> > static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
>> > {
>> > - return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
>> > + return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) &
>> > DPFC_COMP_SEG_MASK;
>> > }
>> >
>> > static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
>> > {
>> >struct drm_i915_private *i915 = fbc->i915;
>> >
>> > - intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
>> > + intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id),
>> > fbc->compressed_fb.start);
>> > }
>> >
>> > static const struct intel_fbc_funcs ilk_fbc_funcs = {
>> > @@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
>> > {
>> >struct drm_i915_private *i915 = fbc->i915;
>> >
>> > - intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
>> > - intel_de_posting_read(i915, MSG_FBC_REND_STATE);
>> > + intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
>> > + intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
>> > }
>> >
>> > static const struct intel_fbc_funcs snb_fbc_funcs = {
>> > @@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct
>> > intel_fbc *fbc)
>> >val |= FBC_STRIDE_OVERRIDE |
>> >FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
>> >
>> > - intel_de_write(i915, GLK_FBC_STRIDE, val);
>> > + intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
>> > }
>> >
>> > static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
>> > @@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
>> >if (i915->ggtt.num_fences)
>> >snb_fbc_program_fence(fbc);
>> >
>> > - intel_de_write(i915, ILK_DPFC_CONTROL,
>> > + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
>> > DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
>> > }
>> >
>> > static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
>> > {
>> > - return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) &
>> > DPFC_COMP_SEG_MASK_IVB;
>> > + return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) &
>> > DPFC_COMP_SEG_MASK_IVB;
>> > }
>> >
>> > static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
>> >bool enable)
>> > {
>> > - intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
>> > + intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
>> > DPFC_CTL_FALSE_COLOR, enable ?
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
On Tue, Dec 14, 2021 at 06:25:43PM +0200, Ville Syrjälä wrote: > On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote: > > On Mon, 13 Dec 2021, Ville Syrjala wrote: > > > > This one is only used in gvt, anyway. And that actually makes me wonder > > if this should be breaking the build. Does CI not have gvt enabled? > > Hmm. I thought it was enabled in CI, but maybe not. I've often broken > gvt with register define changes but I've always caught it before > pushing. I think I have gvt enabled in my "make sure all commits build > before I push" test config, so maybe that's where I caught most of them. > > Tomi, can we enable gvt in ci builds to make sure it at least still > builds? Actually cc Tomi.. -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote:
> On Mon, 13 Dec 2021, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Parametrize ilk+ FBC register offsets based on the FBC instance.
> >
> > v2: More intel_ namespace (Jani)
> >
> > Cc: Jani Nikula
> > Signed-off-by: Ville Syrjälä
>
> Some questions below, apart from that,
>
> Reviewed-by: Jani Nikula
>
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 34 +---
> > drivers/gpu/drm/i915/display/intel_fbc.h | 6 +
> > drivers/gpu/drm/i915/i915_reg.h | 34
> > drivers/gpu/drm/i915/intel_pm.c | 31 -
> > 4 files changed, 60 insertions(+), 45 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 8be01b93015f..112aafa72253 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -85,6 +85,8 @@ struct intel_fbc {
> > struct drm_mm_node compressed_fb;
> > struct drm_mm_node compressed_llb;
> >
> > + enum intel_fbc_id id;
> > +
> > u8 limit;
> >
> > bool false_color;
> > @@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
> > struct intel_fbc_state *fbc_state = >state;
> > struct drm_i915_private *i915 = fbc->i915;
> >
> > - intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
> > + intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
> >fbc_state->fence_y_offset);
> >
> > - intel_de_write(i915, ILK_DPFC_CONTROL,
> > + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> >DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
> > }
> >
> > @@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
> > u32 dpfc_ctl;
> >
> > /* Disable compression */
> > - dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
> > + dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
> > if (dpfc_ctl & DPFC_CTL_EN) {
> > dpfc_ctl &= ~DPFC_CTL_EN;
> > - intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
> > + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> > }
> > }
> >
> > static bool ilk_fbc_is_active(struct intel_fbc *fbc)
> > {
> > - return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
> > + return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) &
> > DPFC_CTL_EN;
> > }
> >
> > static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
> > {
> > - return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
> > + return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) &
> > DPFC_COMP_SEG_MASK;
> > }
> >
> > static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
> > {
> > struct drm_i915_private *i915 = fbc->i915;
> >
> > - intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
> > + intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id),
> > fbc->compressed_fb.start);
> > }
> >
> > static const struct intel_fbc_funcs ilk_fbc_funcs = {
> > @@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
> > {
> > struct drm_i915_private *i915 = fbc->i915;
> >
> > - intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
> > - intel_de_posting_read(i915, MSG_FBC_REND_STATE);
> > + intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
> > + intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
> > }
> >
> > static const struct intel_fbc_funcs snb_fbc_funcs = {
> > @@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc
> > *fbc)
> > val |= FBC_STRIDE_OVERRIDE |
> > FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
> >
> > - intel_de_write(i915, GLK_FBC_STRIDE, val);
> > + intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
> > }
> >
> > static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
> > @@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
> > if (i915->ggtt.num_fences)
> > snb_fbc_program_fence(fbc);
> >
> > - intel_de_write(i915, ILK_DPFC_CONTROL,
> > + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> >DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
> > }
> >
> > static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
> > {
> > - return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) &
> > DPFC_COMP_SEG_MASK_IVB;
> > + return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) &
> > DPFC_COMP_SEG_MASK_IVB;
> > }
> >
> > static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
> > bool enable)
> > {
> > - intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
> > + intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
> > DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
> > }
> >
> > @@ -1620,7 +1622,8 @@ void intel_fbc_add_plane(struct intel_fbc *fbc,
> > struct intel_plane
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
On Mon, 13 Dec 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Parametrize ilk+ FBC register offsets based on the FBC instance.
>
> v2: More intel_ namespace (Jani)
>
> Cc: Jani Nikula
> Signed-off-by: Ville Syrjälä
Some questions below, apart from that,
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 34 +---
> drivers/gpu/drm/i915/display/intel_fbc.h | 6 +
> drivers/gpu/drm/i915/i915_reg.h | 34
> drivers/gpu/drm/i915/intel_pm.c | 31 -
> 4 files changed, 60 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 8be01b93015f..112aafa72253 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -85,6 +85,8 @@ struct intel_fbc {
> struct drm_mm_node compressed_fb;
> struct drm_mm_node compressed_llb;
>
> + enum intel_fbc_id id;
> +
> u8 limit;
>
> bool false_color;
> @@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
> struct intel_fbc_state *fbc_state = >state;
> struct drm_i915_private *i915 = fbc->i915;
>
> - intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
> + intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
> fbc_state->fence_y_offset);
>
> - intel_de_write(i915, ILK_DPFC_CONTROL,
> + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
> }
>
> @@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
> u32 dpfc_ctl;
>
> /* Disable compression */
> - dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
> + dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
> if (dpfc_ctl & DPFC_CTL_EN) {
> dpfc_ctl &= ~DPFC_CTL_EN;
> - intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
> + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> }
> }
>
> static bool ilk_fbc_is_active(struct intel_fbc *fbc)
> {
> - return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
> + return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) &
> DPFC_CTL_EN;
> }
>
> static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
> {
> - return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
> + return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) &
> DPFC_COMP_SEG_MASK;
> }
>
> static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
> {
> struct drm_i915_private *i915 = fbc->i915;
>
> - intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
> + intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id),
> fbc->compressed_fb.start);
> }
>
> static const struct intel_fbc_funcs ilk_fbc_funcs = {
> @@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
> {
> struct drm_i915_private *i915 = fbc->i915;
>
> - intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
> - intel_de_posting_read(i915, MSG_FBC_REND_STATE);
> + intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
> + intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
> }
>
> static const struct intel_fbc_funcs snb_fbc_funcs = {
> @@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc
> *fbc)
> val |= FBC_STRIDE_OVERRIDE |
> FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
>
> - intel_de_write(i915, GLK_FBC_STRIDE, val);
> + intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
> }
>
> static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
> @@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
> if (i915->ggtt.num_fences)
> snb_fbc_program_fence(fbc);
>
> - intel_de_write(i915, ILK_DPFC_CONTROL,
> + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
> }
>
> static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
> {
> - return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) &
> DPFC_COMP_SEG_MASK_IVB;
> + return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) &
> DPFC_COMP_SEG_MASK_IVB;
> }
>
> static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
> bool enable)
> {
> - intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
> + intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
>DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
> }
>
> @@ -1620,7 +1622,8 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, struct
> intel_plane *plane)
> fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
> }
>
> -static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
> +static struct intel_fbc *intel_fbc_create(struct drm_i915_private
[Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
From: Ville Syrjälä
Parametrize ilk+ FBC register offsets based on the FBC instance.
v2: More intel_ namespace (Jani)
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 34 +---
drivers/gpu/drm/i915/display/intel_fbc.h | 6 +
drivers/gpu/drm/i915/i915_reg.h | 34
drivers/gpu/drm/i915/intel_pm.c | 31 -
4 files changed, 60 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8be01b93015f..112aafa72253 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -85,6 +85,8 @@ struct intel_fbc {
struct drm_mm_node compressed_fb;
struct drm_mm_node compressed_llb;
+ enum intel_fbc_id id;
+
u8 limit;
bool false_color;
@@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
struct intel_fbc_state *fbc_state = >state;
struct drm_i915_private *i915 = fbc->i915;
- intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
+ intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
fbc_state->fence_y_offset);
- intel_de_write(i915, ILK_DPFC_CONTROL,
+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
}
@@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
u32 dpfc_ctl;
/* Disable compression */
- dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
+ dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
if (dpfc_ctl & DPFC_CTL_EN) {
dpfc_ctl &= ~DPFC_CTL_EN;
- intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
}
}
static bool ilk_fbc_is_active(struct intel_fbc *fbc)
{
- return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
+ return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) &
DPFC_CTL_EN;
}
static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
{
- return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
+ return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) &
DPFC_COMP_SEG_MASK;
}
static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
- intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
+ intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id),
fbc->compressed_fb.start);
}
static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
- intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
- intel_de_posting_read(i915, MSG_FBC_REND_STATE);
+ intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
+ intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
}
static const struct intel_fbc_funcs snb_fbc_funcs = {
@@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc
*fbc)
val |= FBC_STRIDE_OVERRIDE |
FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
- intel_de_write(i915, GLK_FBC_STRIDE, val);
+ intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
}
static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
@@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
if (i915->ggtt.num_fences)
snb_fbc_program_fence(fbc);
- intel_de_write(i915, ILK_DPFC_CONTROL,
+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
}
static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
{
- return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) &
DPFC_COMP_SEG_MASK_IVB;
+ return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) &
DPFC_COMP_SEG_MASK_IVB;
}
static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
bool enable)
{
- intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
+ intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
}
@@ -1620,7 +1622,8 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, struct
intel_plane *plane)
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
-static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
+static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
+ enum intel_fbc_id fbc_id)
{
struct intel_fbc *fbc;
@@ -1628,6 +1631,7 @@ static struct intel_fbc *intel_fbc_create(struct
drm_i915_private *i915)
if (!fbc)
return NULL;
+ fbc->id
